ARM: keystone2: Use common structure for PLLs

Register Base addresses are same for PLLs in all
keystone platforms. If a PLL is not available, the corresponding
register addresses are marked as reserved.
Hence use a common definition.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/mach-keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c
index 42092e1060dfce095487f83bd73e578e03525013..b23d2a561edd9c60b6d8ae9f235109c04ed3eb30 100644 (file)
--- a/arch/arm/mach-keystone/clock-k2e.c
+++ b/arch/arm/mach-keystone/clock-k2e.c
@@ -11,12 +11,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
-const struct keystone_pll_regs keystone_pll_regs[] = {
-       [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
-       [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
-       [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD

diff --git a/arch/arm/mach-keystone/clock-k2hk.c b/arch/arm/mach-keystone/clock-k2hk.c
index 96a9f7288613987e9da61204caa6b4801cedf3d2..2e368910bf050d2f9c1cacc3ba05661edc8e3bbc 100644 (file)
--- a/arch/arm/mach-keystone/clock-k2hk.c
+++ b/arch/arm/mach-keystone/clock-k2hk.c
@@ -11,14 +11,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
-const struct keystone_pll_regs keystone_pll_regs[] = {
-       [CORE_PLL]      = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
-       [PASS_PLL]      = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
-       [TETRIS_PLL]    = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
-       [DDR3A_PLL]     = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-       [DDR3B_PLL]     = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
-};
-
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD

diff --git a/arch/arm/mach-keystone/clock-k2l.c b/arch/arm/mach-keystone/clock-k2l.c
index 80c1f5134a4bd3c94cd79443b1273bd6a47ea23e..0bd0fd6ac29e5b6e49de8913288a90c1decda388 100644 (file)
--- a/arch/arm/mach-keystone/clock-k2l.c
+++ b/arch/arm/mach-keystone/clock-k2l.c
@@ -11,13 +11,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
-const struct keystone_pll_regs keystone_pll_regs[] = {
-       [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
-       [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
-       [TETRIS_PLL] = {KS2_ARMPLLCTL0,  KS2_ARMPLLCTL1},
-       [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD

diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index aaeef79bd3969ff6fe634acf8db9bb36556da18b..de5dfe15eb9340842bc21203e2923185c8947711 100644 (file)
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -25,6 +25,14 @@ int __weak speeds[DEVSPEED_NUMSPDS] = {
        SPD800,
 };
 
+const struct keystone_pll_regs keystone_pll_regs[] = {
+       [CORE_PLL]      = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+       [PASS_PLL]      = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+       [TETRIS_PLL]    = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+       [DDR3A_PLL]     = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+       [DDR3B_PLL]     = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+};
+
 static void wait_for_completion(const struct pll_init_data *data)
 {
        int i;

diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h
index 6f53e43f0ae16c99b80b879c84d003e907b2d874..8fdc0f0e8358f3d755cfcbe02948aebdd1c63cab 100644 (file)
--- a/arch/arm/mach-keystone/include/mach/clock-k2e.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h
@@ -50,14 +50,6 @@ extern unsigned int external_clk[ext_clk_count];
 
 #define KS2_CLK1_6     sys_clk0_6_clk
 
-/* PLL identifiers */
-enum pll_type_e {
-       CORE_PLL,
-       PASS_PLL,
-       DDR3_PLL,
-       TETRIS_PLL,
-};
-
 #define CORE_PLL_800   {CORE_PLL, 16, 1, 2}
 #define CORE_PLL_850   {CORE_PLL, 17, 1, 2}
 #define CORE_PLL_1000  {CORE_PLL, 20, 1, 2}

diff --git a/arch/arm/mach-keystone/include/mach/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
index c41210c134e31ac862fe1960247e892a7ce95167..366bf0ee593bcdf06a4bf525605412658722d729 100644 (file)
--- a/arch/arm/mach-keystone/include/mach/clock-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
@@ -55,15 +55,6 @@ extern unsigned int external_clk[ext_clk_count];
 
 #define KS2_CLK1_6 sys_clk0_6_clk
 
-/* PLL identifiers */
-enum pll_type_e {
-       CORE_PLL,
-       PASS_PLL,
-       TETRIS_PLL,
-       DDR3A_PLL,
-       DDR3B_PLL,
-};
-
 #define CORE_PLL_799    {CORE_PLL,     13,     1,      2}
 #define CORE_PLL_983    {CORE_PLL,     16,     1,      2}
 #define CORE_PLL_999   {CORE_PLL,      122,    15,     1}

diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h
index c145a1eeb0bd48434cb619b3a1a4e25509685812..e3f005a72cdd36ddf53b191b1c80b13ff05c2300 100644 (file)
--- a/arch/arm/mach-keystone/include/mach/clock-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h
@@ -51,14 +51,6 @@ extern unsigned int external_clk[ext_clk_count];
 
 #define KS2_CLK1_6     sys_clk0_6_clk
 
-/* PLL identifiers */
-enum pll_type_e {
-       CORE_PLL,
-       PASS_PLL,
-       TETRIS_PLL,
-       DDR3_PLL,
-};
-
 #define CORE_PLL_799   {CORE_PLL, 13, 1, 2}
 #define CORE_PLL_983   {CORE_PLL, 16, 1, 2}
 #define CORE_PLL_1000  {CORE_PLL, 114, 7, 2}

diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index cb2b43c937fa2485588bf686343f2f5509b61710..9ba4463224e1fb6d082a7a3ce678fed7f634b2d5 100644 (file)
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -24,7 +24,8 @@
 #include <asm/arch/clock-k2l.h>
 #endif
 
-#define MAIN_PLL CORE_PLL
+#define CORE_PLL MAIN_PLL
+#define DDR3_PLL DDR3A_PLL
 
 #include <asm/types.h>
 
@@ -44,6 +45,16 @@ enum {
        NUM_SPDS,
 };
 
+/* PLL identifiers */
+enum {
+       MAIN_PLL,
+       TETRIS_PLL,
+       PASS_PLL,
+       DDR3A_PLL,
+       DDR3B_PLL,
+       MAX_PLL_COUNT,
+};
+
 enum clk_e {
        CLK_LIST(GENERATE_ENUM)
 };

diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2hk.h b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h
index 195c0d300396dbed07898089595e676c761ee791..8c771dc336e1cb48085da69a03d76cbfe4fe55a4 100644 (file)
--- a/arch/arm/mach-keystone/include/mach/hardware-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h
@@ -15,10 +15,6 @@
 /* PA SS Registers */
 #define KS2_PASS_BASE                  0x02000000
 
-/* PLL control registers */
-#define KS2_DDR3BPLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
-#define KS2_DDR3BPLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
-
 /* Power and Sleep Controller (PSC) Domains */
 #define KS2_LPSC_MOD                   0
 #define KS2_LPSC_DUMMY1                        1

diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index cf32ae547a7efb80a1a0dd5f14bf51ea50f9a4a7..53f28ec8daf1712e37497ba55f3b6141bc917da7 100644 (file)
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -165,6 +165,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_PASSPLLCTL1                        (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
 #define KS2_DDR3APLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
 #define KS2_DDR3APLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
+#define KS2_DDR3BPLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
+#define KS2_DDR3BPLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
 #define KS2_ARMPLLCTL0                 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
 #define KS2_ARMPLLCTL1                 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)