#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24))
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#define CORE_AVS_CONTROL_0REG 0x18300
#define CORE_AVS_CONTROL_2REG 0x18308
#define CPU_AVS_CONTROL2_REG 0x20868
#define MSAR_TCLK_OFFS 28
#define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS)
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/* Controler environment registers offsets */
#define GEN_PURP_RES_1_REG 0x182F4
#define GEN_PURP_RES_2_REG 0x182F8
0x40000 + ((port) % 2) * 0x4000)
#define MV_ETH_REGS_BASE(port) MV_ETH_REGS_OFFSET(port)
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#define SGMII_PWR_PLL_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xE04)
#define SGMII_DIG_LP_ENA_REG(port) (MV_ETH_REGS_BASE(port) + 0xE8C)
#define SGMII_REF_CLK_SEL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF18)
#define SCR_PEX1_4BY1_OFFS 8
#define SCR_PEX1_4BY1_MASK (1 << SCR_PEX1_4BY1_OFFS)
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#define MV_MISC_REGS_OFFSET (0x18200)
#define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET)
#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS)
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#define PEX_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x60)
#define PEX_LINK_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x6C)
#define PEX_LINK_CTRL_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x70)
SERDES_LAST_UNIT
} MV_BIN_SERDES_UNIT_INDX;
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typedef enum {
PEX_BUS_DISABLED = 0,
PEX_BUS_MODE_X1 = 1,
MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
} MV_BIN_SERDES_CFG;
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#define BIN_SERDES_CFG { \
{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
{0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \