clk: rockchip: rk3588: add hardcoded assigned clocks values

The CRU is being probed with a default set of assigned clocks, which
are not implemented in the driver at all.
Hence, when clk_set_defaults is called, it fails with ENOENT.
This would not be a problem, as the CRU still handles all the required
clocks, and the assigned clocks are default configs which are preprogrammed
or not required for Uboot operations.
However, the rockchip reset driver is being bound by the same DT node
as CRU, as the reset driver has no DT node.
But, when probing the reset node, it will call again the clk_set_defaults
for the CRU node, and failing because of missing those specific clocks
in the rk3588 clock driver.
To avoid this, simply implement a basic set/get that will just return
success and the default corresponding rate for the required assigned clocks.
As those clocks were not supported in Uboot, not required for Uboot
operations, there is no need to do any different kind of initialization.

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
index f5a4592b469f31fae8078fe75af6c3f082520f8d..5c27626df78dcf41854e8250b381286485b1b10c 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -1557,6 +1557,21 @@ static ulong rk3588_clk_get_rate(struct clk *clk)
        case TCLK_WDT0:
                rate = OSC_HZ;
                break;
+       case PCLK_PMU0_ROOT:
+               rate = 100000000;
+               break;
+       case HCLK_PMU_CM0_ROOT:
+               rate = 200000000;
+               break;
+       case ACLK_BUS_ROOT:
+               rate = 375000000;
+               break;
+       case CLK_150M_SRC:
+               rate = 150000000;
+               break;
+       case CLK_GPU:
+               rate = 200000000;
+               break;
 #ifndef CONFIG_SPL_BUILD
        case CLK_AUX16M_0:
        case CLK_AUX16M_1:
@@ -1707,6 +1722,13 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate)
        case TCLK_WDT0:
                ret = OSC_HZ;
                break;
+       case PCLK_PMU0_ROOT:
+       case CLK_GPU:
+       case HCLK_PMU_CM0_ROOT:
+       case ACLK_BUS_ROOT:
+       case CLK_150M_SRC:
+               ret = 0;
+               break;
 #ifndef CONFIG_SPL_BUILD
        case CLK_AUX16M_0:
        case CLK_AUX16M_1: