]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
arch: layerscape: Add SFP binding
authorSean Anderson <sean.anderson@seco.com>
Fri, 22 Apr 2022 18:34:20 +0000 (14:34 -0400)
committerPeng Fan <peng.fan@nxp.com>
Mon, 20 Jun 2022 01:18:26 +0000 (09:18 +0800)
This adds an SFP binding for the processors it is present on. I have
only tested this for the LS1046A.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
arch/arm/dts/fsl-ls1012a.dtsi
arch/arm/dts/fsl-ls1043a.dtsi
arch/arm/dts/fsl-ls1046a.dtsi
arch/arm/dts/ls1021a.dtsi

index 1cdcc99c1ee65a4f077e04dd9ef13e2cefa12eec..796d72fc9edb91f230883aa80dde434ff59747d9 100644 (file)
                #size-cells = <2>;
                ranges;
 
+               sfp: efuse@1e80000 {
+                       compatible = "fsl,ls1021a-sfp";
+                       reg = <0x0 0x1e80000 0x0 0x1000>;
+                       clocks = <&clockgen 4 3>;
+                       clock-names = "sfp";
+               };
+
                clockgen: clocking@1ee1000 {
                        compatible = "fsl,ls1012a-clockgen";
                        reg = <0x0 0x1ee1000 0x0 0x1000>;
index 72877d2ff58e5201e529236c468b25c576095ff0..4960973a60355806f3bd82ed883788fa0b9f476e 100644 (file)
                #size-cells = <2>;
                ranges;
 
+               sfp: efuse@1e80000 {
+                       compatible = "fsl,ls1021a-sfp";
+                       reg = <0x0 0x1e80000 0x0 0x1000>;
+                       clocks = <&clockgen 4 3>;
+                       clock-names = "sfp";
+               };
+
                clockgen: clocking@1ee1000 {
                        compatible = "fsl,ls1043a-clockgen";
                        reg = <0x0 0x1ee1000 0x0 0x1000>;
index c655e002aa0825e56b51186cee9438dd66f379ef..060dc399c2f6b939ae9c501514951b9c8c4f2df4 100644 (file)
                #size-cells = <2>;
                ranges;
 
+               sfp: efuse@1e80000 {
+                       compatible = "fsl,ls1021a-sfp";
+                       reg = <0x0 0x1e80000 0x0 0x1000>;
+                       clocks = <&clockgen 4 3>;
+                       clock-names = "sfp";
+               };
+
                clockgen: clocking@1ee1000 {
                        compatible = "fsl,ls1046a-clockgen";
                        reg = <0x0 0x1ee1000 0x0 0x1000>;
index 063655f7ac65a9880cd278b01317bcd3930fb085..4f65ee765e3f228536c36ebca9315c17376483ff 100644 (file)
                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               sfp: efuse@1e80000 {
+                       compatible = "fsl,ls1021a-sfp";
+                       reg = <0x0 0x1e80000 0x0 0x10000>;
+                       clocks = <&clockgen 4 3>;
+                       clock-names = "sfp";
+               };
+
                dcfg: dcfg@1ee0000 {
                        compatible = "fsl,ls1021a-dcfg", "syscon";
                        reg = <0x1ee0000 0x10000>;