]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
ARM: dts: stm32: add cpufreq support on stm32mp15x
authorPatrick Delaunay <patrick.delaunay@st.com>
Mon, 25 May 2020 10:19:42 +0000 (12:19 +0200)
committerPatrick Delaunay <patrick.delaunay@st.com>
Tue, 7 Jul 2020 14:01:23 +0000 (16:01 +0200)
This commit adds cpufreq support on stm32mp15x SOC. STM32 cpufreq uses
operating points V2 bindings (no legacy). Nvmem cells have to be used to
know the chip version and then which OPPs are available. Note that STM32
cpufreq driver is mainly based on "cpufreq-dt" driver.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
arch/arm/dts/stm32mp151.dtsi
arch/arm/dts/stm32mp157c-ed1.dts
arch/arm/dts/stm32mp15xx-dkx.dtsi

index 75d2c0d296efc509b77fce17730a284da19ca093..d5216a18313ce51b284d8d1d4c599805af42ae0e 100644 (file)
                        clock-frequency = <650000000>;
                        device_type = "cpu";
                        reg = <0>;
+                       operating-points-v2 = <&cpu0_opp_table>;
+                       nvmem-cells = <&part_number_otp>;
+                       nvmem-cell-names = "part_number";
+               };
+       };
+
+       cpu0_opp_table: cpu0-opp-table {
+               compatible = "operating-points-v2";
+               opp-shared;
+               opp-650000000 {
+                       opp-hz = /bits/ 64 <650000000>;
+                       opp-microvolt = <1200000>;
+                       opp-supported-hw = <0x1>;
+               };
+               opp-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-microvolt = <1350000>;
+                       opp-supported-hw = <0x2>;
                };
        };
 
                        reg = <0x5c005000 0x400>;
                        #address-cells = <1>;
                        #size-cells = <1>;
+                       part_number_otp: part_number_otp@4 {
+                               reg = <0x4 0x1>;
+                       };
                        ts_cal1: calib@5c {
                                reg = <0x5c 0x2>;
                        };
index 186dc46754432bcf9f3665fd8f92fd83ac5e8b7d..c4c1202789d3ad1306c6c1a33815a53ae427be79 100644 (file)
        };
 };
 
+&cpu0{
+       cpu-supply = <&vddcore>;
+};
+
+&cpu1{
+       cpu-supply = <&vddcore>;
+};
+
 &dac {
        pinctrl-names = "default";
        pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
index 7589c6f9dc5a44c263ca9de7506be7b4e396ba19..e7a46e7b5fb1713b50c1b0b7de841093f8febecb 100644 (file)
        status = "okay";
 };
 
+&cpu0{
+       cpu-supply = <&vddcore>;
+};
+
+&cpu1{
+       cpu-supply = <&vddcore>;
+};
+
 &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rgmii_pins_a>;