mvebu: pcie: Add support for GPIO reset for PCIe device

Add support for "marvell,reset-gpio" property to mvebu DW PCIe
driver.
This option is valid when CONFIG_DM_GPIO=y

Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/doc/device-tree-bindings/pci/armada8k-pcie.txt b/doc/device-tree-bindings/pci/armada8k-pcie.txt
new file mode 100644 (file)
index 0000000..7230f10
--- /dev/null
+++ b/doc/device-tree-bindings/pci/armada8k-pcie.txt
@@ -0,0 +1,49 @@
+Armada-8K PCIe DT details:
+==========================
+
+Armada-8k uses synopsis designware PCIe controller.
+
+Required properties:
+- compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie".
+- reg: base addresses and lengths of the pcie control and global control registers.
+ "ctrl" registers points to the global control registers, while the "config" space
+ points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below.
+- interrupt-map-mask and interrupt-map, standard PCI properties to
+  define the mapping of the PCIe interface to interrupt numbers.
+- All other definitions as per generic PCI bindings
+See Linux kernel documentation:
+"Documentation/devicetree/bindings/pci/designware-pcie.txt"
+
+Optional properties:
+PHY support is still not supported for armada-8k, once it will, the following parameters can be used:
+- phys             : phandle to phy node associated with pcie controller.
+- phy-names        : must be "pcie-phy"
+- marvell,reset-gpio :  specifies a gpio that needs to be activated for plug-in
+                       card reset signal release.
+Example:
+
+cpm_pcie0: pcie@f2600000 {
+       compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+       reg = <0 0xf2600000 0 0x10000>,
+             <0 0xf6f00000 0 0x80000>;
+       reg-names = "ctrl", "config";
+       #address-cells = <3>;
+       #size-cells = <2>;
+       #interrupt-cells = <1>;
+       device_type = "pci";
+       dma-coherent;
+
+       bus-range = <0 0xff>;
+       ranges =
+               /* downstream I/O */
+               <0x81000000 0 0xf9000000 0  0xf9000000 0 0x10000
+               /* non-prefetchable memory */
+               0x82000000 0 0xf6000000 0  0xf6000000 0 0xf00000>;
+       interrupt-map-mask = <0 0 0 0>;
+       interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+       num-lanes = <1>;
+       clocks = <&cpm_syscon0 1 13>;
+       marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>;
+       status = "disabled";
+};

diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index 17fa0244d007283190cca1fd0622270375a80283..d4776a9c81e693a9eafbdef045e7ddc8aa669a5e 100644 (file)
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -15,6 +15,7 @@
 #include <dm.h>
 #include <pci.h>
 #include <asm/io.h>
+#include <asm-generic/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -461,6 +462,25 @@ static int pcie_dw_mvebu_probe(struct udevice *dev)
        struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
        struct udevice *ctlr = pci_get_controller(dev);
        struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+#ifdef CONFIG_DM_GPIO
+       struct gpio_desc reset_gpio;
+
+       gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio,
+                            GPIOD_IS_OUT);
+       /*
+        * Issue reset to add-in card trough the dedicated GPIO.
+        * Some boards are connecting the card reset pin to common system
+        * reset wire and others are using separate GPIO port.
+        * In the last case we have to release a reset of the addon card
+        * using this GPIO.
+        */
+       if (dm_gpio_is_valid(&reset_gpio)) {
+               dm_gpio_set_value(&reset_gpio, 1);
+               mdelay(200);
+       }
+#else
+       debug("PCIE Reset on GPIO support is missing\n");
+#endif /* CONFIG_DM_GPIO */
 
        pcie->first_busno = dev->seq;