arm: dts: imx8mp: Resync imx8mp device tree include

Sync imx8mp include with kernel commit:
d1689cd3c0f4 ("arm64: dts: imx8mp: Use the correct name for child node "snps, dwc3"")

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index ecccfbb4f5ad6831c5d00af1f56201ad99fe5f9d..c2d51a46cb3cb294e0378f75015a74dbf19f6fcc 100644 (file)
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -18,6 +18,7 @@
 
        aliases {
                ethernet0 = &fec;
+               ethernet1 = &eqos;
                gpio0 = &gpio1;
                gpio1 = &gpio2;
                gpio2 = &gpio3;
@@ -218,10 +219,12 @@
        };
 
        soc@0 {
-               compatible = "simple-bus";
+               compatible = "fsl,imx8mp-soc", "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0x0 0x0 0x0 0x3e000000>;
+               nvmem-cells = <&imx8mp_uid>;
+               nvmem-cell-names = "soc_unique_id";
 
                aips1: bus@30000000 {
                        compatible = "fsl,aips-bus", "simple-bus";
@@ -266,7 +269,7 @@
                                #gpio-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
-                               gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>;
+                               gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
                        };
 
                        gpio4: gpio@30230000 {
@@ -310,6 +313,22 @@
                                status = "disabled";
                        };
 
+                       wdog2: watchdog@30290000 {
+                               compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
+                               reg = <0x30290000 0x10000>;
+                               interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
+                               status = "disabled";
+                       };
+
+                       wdog3: watchdog@302a0000 {
+                               compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
+                               reg = <0x302a0000 0x10000>;
+                               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
+                               status = "disabled";
+                       };
+
                        iomuxc: pinctrl@30330000 {
                                compatible = "fsl,imx8mp-iomuxc";
                                reg = <0x30330000 0x10000>;
@@ -328,9 +347,17 @@
                                #address-cells = <1>;
                                #size-cells = <1>;
 
+                               imx8mp_uid: unique-id@420 {
+                                       reg = <0x8 0x8>;
+                               };
+
                                cpu_speed_grade: speed-grade@10 {
                                        reg = <0x10 4>;
                                };
+
+                               eth_mac1: mac-address@90 {
+                                       reg = <0x90 6>;
+                               };
                        };
 
                        anatop: anatop@30360000 {
@@ -762,13 +789,40 @@
                                assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
                                                  <&clk IMX8MP_CLK_ENET_TIMER>,
                                                  <&clk IMX8MP_CLK_ENET_REF>,
-                                                 <&clk IMX8MP_CLK_ENET_TIMER>;
+                                                 <&clk IMX8MP_CLK_ENET_PHY_REF>;
                                assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
                                                         <&clk IMX8MP_SYS_PLL2_100M>,
-                                                        <&clk IMX8MP_SYS_PLL2_125M>;
-                               assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+                                                        <&clk IMX8MP_SYS_PLL2_125M>,
+                                                        <&clk IMX8MP_SYS_PLL2_50M>;
+                               assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
                                fsl,num-tx-queues = <3>;
                                fsl,num-rx-queues = <3>;
+                               nvmem-cells = <&eth_mac1>;
+                               nvmem-cell-names = "mac-address";
+                               fsl,stop-mode = <&gpr 0x10 3>;
+                               nvmem_macaddr_swap;
+                               status = "disabled";
+                       };
+
+                       eqos: ethernet@30bf0000 {
+                               compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
+                               reg = <0x30bf0000 0x10000>;
+                               interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "eth_wake_irq", "macirq";
+                               clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
+                                        <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
+                                        <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
+                                        <&clk IMX8MP_CLK_ENET_QOS>;
+                               clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
+                               assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
+                                                 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
+                                                 <&clk IMX8MP_CLK_ENET_QOS>;
+                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
+                                                        <&clk IMX8MP_SYS_PLL2_100M>,
+                                                        <&clk IMX8MP_SYS_PLL2_125M>;
+                               assigned-clock-rates = <0>, <100000000>, <125000000>;
+                               intf_mode = <&gpr 0x4>;
                                status = "disabled";
                        };
                };
@@ -788,5 +842,87 @@
                        reg = <0x3d800000 0x400000>;
                        interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
                };
+
+               usb3_phy0: usb-phy@381f0040 {
+                       compatible = "fsl,imx8mp-usb-phy";
+                       reg = <0x381f0040 0x40>;
+                       clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+                       clock-names = "phy";
+                       assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+                       assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+                       #phy-cells = <0>;
+                       status = "disabled";
+               };
+
+               usb3_0: usb@32f10100 {
+                       compatible = "fsl,imx8mp-dwc3";
+                       reg = <0x32f10100 0x8>;
+                       clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+                                <&clk IMX8MP_CLK_USB_ROOT>;
+                       clock-names = "hsio", "suspend";
+                       interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       dma-ranges = <0x40000000 0x40000000 0xc0000000>;
+                       ranges;
+                       status = "disabled";
+
+                       usb_dwc3_0: usb@38100000 {
+                               compatible = "snps,dwc3";
+                               reg = <0x38100000 0x10000>;
+                               clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+                                        <&clk IMX8MP_CLK_USB_CORE_REF>,
+                                        <&clk IMX8MP_CLK_USB_ROOT>;
+                               clock-names = "bus_early", "ref", "suspend";
+                               assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+                               assigned-clock-rates = <500000000>;
+                               interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+                               phys = <&usb3_phy0>, <&usb3_phy0>;
+                               phy-names = "usb2-phy", "usb3-phy";
+                               snps,dis-u2-freeclk-exists-quirk;
+                       };
+
+               };
+
+               usb3_phy1: usb-phy@382f0040 {
+                       compatible = "fsl,imx8mp-usb-phy";
+                       reg = <0x382f0040 0x40>;
+                       clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+                       clock-names = "phy";
+                       assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+                       assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+                       #phy-cells = <0>;
+               };
+
+               usb3_1: usb@32f10108 {
+                       compatible = "fsl,imx8mp-dwc3";
+                       reg = <0x32f10108 0x8>;
+                       clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+                                <&clk IMX8MP_CLK_USB_ROOT>;
+                       clock-names = "hsio", "suspend";
+                       interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       dma-ranges = <0x40000000 0x40000000 0xc0000000>;
+                       ranges;
+                       status = "disabled";
+
+                       usb_dwc3_1: usb@38200000 {
+                               compatible = "snps,dwc3";
+                               reg = <0x38200000 0x10000>;
+                               clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+                                        <&clk IMX8MP_CLK_USB_CORE_REF>,
+                                        <&clk IMX8MP_CLK_USB_ROOT>;
+                               clock-names = "bus_early", "ref", "suspend";
+                               assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+                               assigned-clock-rates = <500000000>;
+                               interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+                               phys = <&usb3_phy1>, <&usb3_phy1>;
+                               phy-names = "usb2-phy", "usb3-phy";
+                               snps,dis-u2-freeclk-exists-quirk;
+                       };
+               };
        };
 };