clk: sandbox: Adjust clk-divider to emulate reading its value from HW

The generic divider clock code for CCF requires reading the divider value
from HW registers. As sandbox by design has readl() as no-op it was
necessary to provide this value in the other way.

The new field in the divider structure (accessible only when sandbox is
run) has been introduced for this purpose.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 3348d97829b205bbab148f3776c0ee074fc19c8b..6921c76a48fc149bb81a80aa5e6b1e2e80b57d19 100644 (file)
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -74,7 +74,12 @@ static ulong clk_divider_recalc_rate(struct clk *clk)
        unsigned long parent_rate = clk_get_parent_rate(clk);
        unsigned int val;
 
-       val = readl(divider->reg) >> divider->shift;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+       val = divider->io_divider_val;
+#else
+       val = readl(divider->reg);
+#endif
+       val >>= divider->shift;
        val &= clk_div_mask(divider->width);
 
        return divider_recalc_rate(clk, parent_rate, val, divider->table,
@@ -112,6 +117,9 @@ static struct clk *_register_divider(struct device *dev, const char *name,
        div->width = width;
        div->flags = clk_divider_flags;
        div->table = table;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+       div->io_divider_val = *(u32 *)reg;
+#endif
 
        /* register the clock */
        clk = &div->clk;

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index e06487f07b4c1331063d0cbaadd7a7e1f196a816..53c9c41b90de4f5870b6ca8a3b26284437f27d50 100644 (file)
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -75,6 +75,9 @@ struct clk_divider {
        u8              width;
        u8              flags;
        const struct clk_div_table      *table;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+       u32             io_divider_val;
+#endif
 };
 
 #define clk_div_mask(width)    ((1 << (width)) - 1)