apalis_t30: describe pcie ports

Add some more comments describing the various PCIe ports available.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 0b84dae2157f655d990f5aa7154872f4e3479dec..0852d8dc53cee784773b05bf70fcfc91086ffbad 100644 (file)
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -43,16 +43,19 @@
                vddio-pex-ctl-supply = <&sys_3v3_reg>;
                hvdd-pex-supply = <&sys_3v3_reg>;
 
+               /* Apalis Type Specific 4 Lane PCIe */
                pci@1,0 {
                        /* TS_DIFF1/2/3/4 left disabled */
                        nvidia,num-lanes = <4>;
                };
 
+               /* Apalis PCIe */
                pci@2,0 {
                        /* PCIE1_RX/TX left disabled */
                        nvidia,num-lanes = <1>;
                };
 
+               /* I210 Gigabit Ethernet Controller (On-module) */
                pci@3,0 {
                        status = "okay";
                        nvidia,num-lanes = <1>;