clk/qcom: sdm845: enable SDCC2 core clock

Allow setting the clock rate for the SD card core clock. This is
required for SD card support on SDM845 devices.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>

diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index cc170d8e3f9e9e72044edd6c4d63f83f62d20a9c..f6445c8f566f1803f095ca0dd0bfdfdf848d95a0 100644 (file)
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -13,6 +13,7 @@
 #define CFG_CLK_SRC_GPLL9 (2 << 8)
 #define CFG_CLK_SRC_GPLL6 (4 << 8)
 #define CFG_CLK_SRC_GPLL7 (3 << 8)
+#define CFG_CLK_SRC_GPLL4 (5 << 8)
 #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
 #define CFG_CLK_SRC_MASK  (7 << 8)
 

diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index e9c61eb480de509a5178a8498d2afc019b18fd75..782df7da8444fac96b1be98d2876cfc3c769d0bf 100644 (file)
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -24,6 +24,7 @@
 #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018
 #define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf030
 #define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf05c
+#define SDCC2_APPS_CLK_CMD_RCGR 0x1400c
 
 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
        F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
@@ -44,6 +45,17 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
        { }
 };
 
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+       F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
+       F(9600000, CFG_CLK_SRC_CXO, 2, 0, 0),
+       F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+       F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+       F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
+       F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+       F(201500000, CFG_CLK_SRC_GPLL4, 4, 0, 0),
+       { }
+};
+
 static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate)
 {
        struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -55,6 +67,11 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate)
                clk_rcg_set_rate_mnd(priv->base, SE9_UART_APPS_CMD_RCGR,
                                     freq->pre_div, freq->m, freq->n, freq->src, 16);
                return freq->freq;
+       case GCC_SDCC2_APPS_CLK:
+               freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
+               clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR,
+                                    freq->pre_div, freq->m, freq->n, freq->src, 8);
+               return freq->freq;
        default:
                return 0;
        }