struct emac_dma_desc *desc_p;
u32 idx;
- /* flush Rx buffers */
- flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
- RX_TOTAL_BUFSIZE);
+ /*
+ * Make sure we don't have dirty cache lines around, which could
+ * be cleaned to DRAM *after* the MAC has already written data to it.
+ */
+ invalidate_dcache_range((uintptr_t)desc_table_p,
+ (uintptr_t)desc_table_p + sizeof(priv->rx_chain));
+ invalidate_dcache_range((uintptr_t)rxbuffs,
+ (uintptr_t)rxbuffs + sizeof(priv->rxbuffer));
for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
;
desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
- desc_p->ctl_size |= CONFIG_ETH_RXSIZE;
+ desc_p->ctl_size = CONFIG_ETH_RXSIZE;
desc_p->status = EMAC_DESC_OWN_DMA;
}