ARMv8/fsl-layerscape: Correct the OCRAM size

The real size of OCRAM is 128KiB, so correct the size of OCRAM.
And OCRAM reserved 2MiB space, then add a new macro to describe
it, which is used for MMU setup.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 6073d442dfd3145e4ebd2e5f946fbcb0eed7fd1e..b3818723eeb699a0fb69d44879e9bbcfee4fcec3 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -28,8 +28,9 @@
 #define CONFIG_FSL_TZASC_400
 #endif
 
-#define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000      /* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE      0x00200000      /* 2M */
+#define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE       0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE      0x00020000 /* Real size 128K */
 
 /* DDR */
 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
@@ -122,7 +123,8 @@
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 #elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE              0x00200000 /* 2M */
+#define SYS_FSL_OCRAM_SPACE_SIZE               0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE              0x00020000 /* Real size 128K */
 
 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
 #define CONFIG_SYS_FSL_ESDHC_BE

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index a97be5c098a23ec203a711b6bf9e98c4db16c0cf..4ea4aeaf4c238886da0d8389eba131ab539ec4e3 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -93,7 +93,7 @@ static struct mm_region early_map[] = {
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-         CONFIG_SYS_FSL_OCRAM_SIZE,
+         SYS_FSL_OCRAM_SPACE_SIZE,
          PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
        },
        { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
@@ -140,7 +140,7 @@ static struct mm_region early_map[] = {
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-         CONFIG_SYS_FSL_OCRAM_SIZE,
+         SYS_FSL_OCRAM_SPACE_SIZE,
          PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
        },
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
@@ -178,7 +178,7 @@ static struct mm_region final_map[] = {
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-         CONFIG_SYS_FSL_OCRAM_SIZE,
+         SYS_FSL_OCRAM_SPACE_SIZE,
          PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
        },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
@@ -280,7 +280,7 @@ static struct mm_region final_map[] = {
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-         CONFIG_SYS_FSL_OCRAM_SIZE,
+         SYS_FSL_OCRAM_SPACE_SIZE,
          PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
        },
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,