This is a low-cost ARMv8 SoC from Socionext Inc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC"
select CPU_V7
+config ARCH_UNIPHIER_LD11
+ bool "UniPhier PH1-LD11 SoC"
+ select ARM64
+ select SPL_SEPARATE_BSS
+
config ARCH_UNIPHIER_LD20
bool "UniPhier PH1-LD20 SoC"
select ARM64
uniphier_pxs2_clk_init();
break;
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+ case SOC_UNIPHIER_LD11:
+ uniphier_ld20_pin_init();
+ led_puts("U1");
+ uniphier_ld11_clk_init();
+ break;
+#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
case SOC_UNIPHIER_LD20:
uniphier_ld20_pin_init();
};
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+static const struct uniphier_board_data uniphier_ld11_data = {
+ .dram_freq = 1600,
+ .dram_nr_ch = 2,
+ .dram_ch[0] = {
+ .base = 0x80000000,
+ .size = 0x20000000,
+ .width = 16,
+ },
+ .dram_ch[1] = {
+ .base = 0xa0000000,
+ .size = 0x20000000,
+ .width = 16,
+ },
+};
+#endif
+
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
static const struct uniphier_board_data uniphier_ld20_data = {
.dram_freq = 1866,
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
{ "socionext,ph1-ld6b", &uniphier_ld6b_data, },
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+ { "socionext,ph1-ld11", &uniphier_ld11_data, },
+#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
{ "socionext,ph1-ld20", &uniphier_ld20_data, },
#endif
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-mode-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-mode-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-mode-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-mode-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-mode-ld20.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
case SOC_UNIPHIER_LD6B:
return uniphier_pxs2_boot_device();
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
+ case SOC_UNIPHIER_LD11:
case SOC_UNIPHIER_LD20:
return uniphier_ld20_boot_device();
#endif
uniphier_pxs2_boot_mode_show();
break;
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
+ case SOC_UNIPHIER_LD11:
case SOC_UNIPHIER_LD20:
uniphier_ld20_boot_mode_show();
break;
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+void uniphier_ld11_clk_init(void)
+{
+ if (readl(SG_PINMON0) & BIT(27)) {
+ /* if booted without stand-by MPU */
+
+ writel(1, SG_ETPHYPSHUT);
+ writel(1, SG_ETPHYCNT);
+
+ udelay(1); /* wait for regulator level 1.1V -> 2.5V */
+
+ writel(3, SG_ETPHYCNT);
+ writel(3, SG_ETPHYPSHUT);
+ writel(7, SG_ETPHYCNT);
+ }
+}
puts("PH1-LD6b (MN2WS0320)");
break;
case 0x31:
- puts("PH1-LD11 ()");
+ puts("PH1-LD11 (SC1405AP1)");
break;
case 0x32:
puts("PH1-LD20 (SC1401AJ1)");
ddrphy-training.o ddrphy-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += umc-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += umc-ld20.o
else
--- /dev/null
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "umc64-regs.h"
+
+#define CONFIG_DDR_FREQ 1866
+
+#define DRAM_CH_NR 2
+
+enum dram_freq {
+ DRAM_FREQ_1600M,
+ DRAM_FREQ_NR,
+};
+
+enum dram_size {
+ DRAM_SZ_256M,
+ DRAM_SZ_512M,
+ DRAM_SZ_NR,
+};
+
+/* umc */
+static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
+static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
+static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
+static u32 umc_cmdctle[DRAM_FREQ_NR] = {0x0078071D};
+static u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
+static u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
+
+static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000810};
+static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000810};
+static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000004};
+static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000004};
+static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
+static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
+
+static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
+ unsigned long size, int ch)
+{
+ writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
+ writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
+ writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
+ writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE);
+ writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
+ writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
+
+ writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
+ writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
+
+ writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
+ writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
+
+ writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
+ writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
+
+ writel(0x00000003, dc_base + UMC_ACSSETA);
+ writel(0x00000103, dc_base + UMC_FLOWCTLG);
+ writel(umc_acssetb[ch], dc_base + UMC_ACSSETB);
+ writel(0x02020200, dc_base + UMC_SPCSETB);
+ writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
+ writel(0x00000002, dc_base + UMC_ACFETCHCTRL);
+
+ return 0;
+}
+
+static int umc_ch_init(void __iomem *umc_ch_base,
+ enum dram_freq freq, unsigned long size, int ch)
+{
+ void __iomem *dc_base = umc_ch_base;
+
+ return umc_dc_init(dc_base, freq, size, ch);
+}
+
+static void um_init(void __iomem *um_base)
+{
+ writel(0x00000001, um_base + UMC_SIORST);
+ writel(0x00000001, um_base + UMC_VO0RST);
+ writel(0x00000001, um_base + UMC_VPERST);
+ writel(0x00000001, um_base + UMC_RGLRST);
+ writel(0x00000001, um_base + UMC_A2DRST);
+ writel(0x00000001, um_base + UMC_DMDRST);
+}
+
+int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
+{
+ void __iomem *um_base = (void __iomem *)0x5B800000;
+ void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
+ enum dram_freq freq;
+ int ch, ret;
+
+ switch (bd->dram_freq) {
+ case 1600:
+ freq = DRAM_FREQ_1600M;
+ break;
+ default:
+ pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
+ return -EINVAL;
+ }
+
+ for (ch = 0; ch < bd->dram_nr_ch; ch++) {
+ unsigned long size = bd->dram_ch[ch].size;
+ unsigned int width = bd->dram_ch[ch].width;
+
+ ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch);
+ if (ret) {
+ pr_err("failed to initialize UMC ch%d\n", ch);
+ return ret;
+ }
+
+ umc_ch_base += 0x00200000;
+ }
+
+ um_init(um_base);
+
+ return 0;
+}
#define UMC_INITSET 0x00000040
#define UMC_INITSTAT 0x00000044
#define UMC_CMDCTLE 0x00000050
+#define UMC_CMDCTLF 0x00000054
+#define UMC_CMDCTLG 0x00000058
#define UMC_SPCSETB 0x00000084
#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
#define UMC_FLOWCTLA 0x00000400
#define UMC_FLOWCTLB 0x00000404
#define UMC_FLOWCTLC 0x00000408
+#define UMC_ACFETCHCTRL 0x00000460
#define UMC_FLOWCTLG 0x00000508
#define UMC_RDATACTL_D0 0x00000600
#define UMC_WDATACTL_D0 0x00000604
#define UMC_ODTCTL_D1 0x0000061C
#define UMC_RESPCTL 0x00000624
#define UMC_DIRECTBUSCTRLA 0x00000680
+#define UMC_DEBUGC 0x00000718
#define UMC_DCCGCTL 0x00000720
#define UMC_DICGCTLA 0x00000724
#define UMC_DICGCTLB 0x00000728
#define UMC_MBUS9 0x00002478
#define UMC_MBUS10 0x000024F8
+/* UMC1 register */
+#define UMC_SIORST 0x00000728
+#define UMC_VO0RST 0x0000073c
+#define UMC_VPERST 0x00000744
+#define UMC_RGLRST 0x00000750
+#define UMC_A2DRST 0x00000764
+#define UMC_DMDRST 0x00000770
+
#endif /* UMC_LD20_REGS_H */
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+
+int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL7);
+ tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30;
+ writel(tmp, SC_RSTCTRL7);
+
+ /* provide clocks */
+ tmp = readl(SC_CLKCTRL4);
+ tmp |= SC_CLKCTRL4_PERI;
+ writel(tmp, SC_CLKCTRL4);
+
+ tmp = readl(SC_CLKCTRL7);
+ tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30;
+ writel(tmp, SC_CLKCTRL7);
+
+ return 0;
+}
#
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-pinctrl-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-pinctrl-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-pinctrl-ld20.o
int uniphier_sld8_init(const struct uniphier_board_data *bd);
int uniphier_pro5_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_init(const struct uniphier_board_data *bd);
int uniphier_ld20_init(const struct uniphier_board_data *bd);
#if defined(CONFIG_MICRO_SUPPORT_CARD)
int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);
void uniphier_sld3_pin_init(void);
void uniphier_ld4_pin_init(void);
void uniphier_pro4_clk_init(void);
void uniphier_pro5_clk_init(void);
void uniphier_pxs2_clk_init(void);
+void uniphier_ld11_clk_init(void);
void uniphier_ld20_clk_init(void);
void cci500_init(int nr_slaves);
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += init-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += init-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += init-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += init-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += init-ld20.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
+
+int uniphier_ld11_init(const struct uniphier_board_data *bd)
+{
+ uniphier_sbc_init_savepin(bd);
+ uniphier_pxs2_sbc_init(bd);
+ uniphier_ld20_early_pin_init(bd);
+
+ support_card_reset();
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+
+ led_puts("L1");
+
+ uniphier_ld11_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ {
+ int res;
+
+ res = uniphier_ld11_umc_init(bd);
+ if (res < 0) {
+ while (1)
+ ;
+ }
+ }
+
+ led_puts("L5");
+
+ dcache_disable();
+
+ led_puts("L6");
+
+ return 0;
+}
uniphier_pxs2_init(param);
break;
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+ case SOC_UNIPHIER_LD11:
+ uniphier_ld11_init(param);
+ break;
+#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
case SOC_UNIPHIER_LD20:
uniphier_ld20_init(param);
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += pinctrl-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += pinctrl-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += pinctrl-ld6b.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pinctrl-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pinctrl-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-savepin.o sbc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o sbc-pxs2.o
#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
+#define SG_ETPHYPSHUT (SG_CTRL_BASE | 0x554)
+#define SG_ETPHYCNT (SG_CTRL_BASE | 0x550)
+
/* Pin Control */
#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_LD11=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld11-ref"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_GPIO_UNIPHIER=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
#define COUNTER_FREQUENCY 50000000
#define CONFIG_GICV3
#define GICD_BASE 0x5fe00000
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+#define GICR_BASE 0x5fe40000
+#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define GICR_BASE 0x5fe80000
+#endif
#else
/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE 1000000
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+#define CONFIG_SPL_STACK (0x30014c00)
+#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_STACK (0x3001c000)
#else
#define CONFIG_SPL_STACK (0x00100000)
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
#define CONFIG_SPL_MAX_SIZE 0x10000
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+#define CONFIG_SPL_BSS_START_ADDR 0x30012000
+#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_BSS_START_ADDR 0x30016000
+#endif
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
projects / u-boot.git / commitdiff