return gd->ram_top;
}
-#endif
+#endif /* CONFIG_ARM64 */
#ifdef CONFIG_SPL_BUILD
static int gpio_init(void)
return 0;
}
SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
-#endif
+#endif /* CONFIG_SPL_BUILD */
#define SUNXI_INVALID_BOOT_SOURCE -1
#endif
sunxi_board_init();
}
-#endif
+#endif /* CONFIG_SPL_BUILD */
#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
while (1) { }
#endif
}
-#endif
+#endif /* CONFIG_SYSRESET */
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A)
void enable_caches(void)
setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE);
#endif
}
-#endif
+#endif /* CONFIG_SPL_BUILD */
void clock_init_sec(void)
{
&ccm->cpu_axi_cfg);
}
}
-#endif
+#endif /* CONFIG_SPL_BUILD */
void clock_set_pll3(unsigned int clk)
{
sunxi_nand_init();
#endif
}
-#endif
+#endif /* CONFIG_NAND_SUNXI */
#ifdef CONFIG_MMC
static void mmc_pinmux_setup(int sdc)
}
}
#endif
-#endif
+#endif /* CONFIG_MMC */
#ifdef CONFIG_SPL_BUILD
else
printf("Failed to set core voltage! Can't set CPU frequency\n");
}
-#endif
+#endif /* CONFIG_SPL_BUILD */
#ifdef CONFIG_USB_GADGET
int g_dnl_board_usb_cable_connected(void)
return sun4i_usb_phy_vbus_detect(&phy);
}
-#endif
+#endif /* CONFIG_USB_GADGET */
#ifdef CONFIG_SERIAL_TAG
void get_board_serial(struct tag_serialnr *serialnr)
}
#ifdef CONFIG_SPL_LOAD_FIT
-
static void set_spl_dt_name(const char *name)
{
struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
return ret;
}
-#endif
+#endif /* CONFIG_SPL_LOAD_FIT */