riscv: cache: use CCTL to flush d-cache

Use CCTL command to do d-cache write back
and invalidate instead of fence.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 8f5455e5195741a50d31a7db4369445f03f38d9d..41de30cc02439f1b1c38930dce5576958ed7218e 100644 (file)
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -8,17 +8,21 @@
 #include <dm.h>
 #include <dm/uclass-internal.h>
 #include <cache.h>
+#include <asm/csr.h>
+
+#ifdef CONFIG_RISCV_NDS_CACHE
+/* mcctlcommand */
+#define CCTL_REG_MCCTLCOMMAND_NUM      0x7cc
+
+/* D-cache operation */
+#define CCTL_L1D_WBINVAL_ALL   6
+#endif
 
 void flush_dcache_all(void)
 {
-       /*
-        * Andes' AX25 does not have a coherence agent. U-Boot must use data
-        * cache flush and invalidate functions to keep data in the system
-        * coherent.
-        * The implementation of the fence instruction in the AX25 flushes the
-        * data cache and is used for this purpose.
-        */
-       asm volatile ("fence" ::: "memory");
+#ifdef CONFIG_RISCV_NDS_CACHE
+       csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
+#endif
 }
 
 void flush_dcache_range(unsigned long start, unsigned long end)
@@ -84,8 +88,8 @@ void dcache_disable(void)
 #ifdef CONFIG_RISCV_NDS_CACHE
        struct udevice *dev = NULL;
 
+       csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
        asm volatile (
-               "fence\n\t"
                "csrr t1, mcache_ctl\n\t"
                "andi t0, t1, ~0x2\n\t"
                "csrw mcache_ctl, t0\n\t"