riscv: jh7110: enable riscv,timer in the device tree

The JH7110 has the arhitectural CPU timer on all 5 rv64 cores.
Note that in the device tree.

Signed-off-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 081b833331bc39c1d71455e9ec43946a7c99cf82..ec237a46ffbaad6e67ca0566b993b4d2b2785fed 100644 (file)
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -163,6 +163,15 @@
                };
        };
 
+       timer {
+               compatible = "riscv,timer";
+               interrupts-extended = <&cpu0_intc 5>,
+                                     <&cpu1_intc 5>,
+                                     <&cpu2_intc 5>,
+                                     <&cpu3_intc 5>,
+                                     <&cpu4_intc 5>;
+       };
+
        osc: oscillator {
                compatible = "fixed-clock";
                clock-output-names = "osc";