net: gem: Remove undocumented is-internal-pcspma dt flag

Generic understanding/consideration is that phy-mode as sgmi means that the
internal PCS(Physical Coding Sublayer) should be enabled by default.
Xilinx GEM implementation allows configuration GEM (gmii mode) + PL PCS PMA
(sgmii mode, Physical Medum Attachment) but in this case phy-mode should be
setup as gmii.
The reason for this assumption is that phy-mode should be described based
on GEM configuration not based on mode coming out of PHY.

Also Linux kernel automatically setting up PCSSEL bit when phy mode is
sgmii without a need to specified additional DT propety.
All our DTSes with sgmii phy mode have this flag enabled that's why there
is no need/reason to just duplicate information.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2ecdbcc4ce692e2f8b3e7054a2abab35f6c03a69.1726213052.git.michal.simek@amd.com

diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts
index 2076271ac9932b57efec895616e090e95615eb8e..1bcf987d7b16777dacd7f3443cacf8a1bf04d9ed 100644 (file)
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@@ -87,7 +87,6 @@
        status = "okay";
        phy-handle = <&phy0>;
        phy-mode = "sgmii"; /* DTG generates this properly  1512 */
-       is-internal-pcspma;
        mdio: mdio {
                #address-cells = <1>;
                #size-cells = <0>;

diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index 0b97fa3f28ac598a436ad1a38940f659d3fd8716..4e0587fd441a23c9826476094cff43c92a6e4c9a 100644 (file)
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -155,7 +155,6 @@
        phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
        phy-handle = <&phy0>;
        phy-mode = "sgmii";
-       is-internal-pcspma;
        mdio: mdio {
                #address-cells = <1>;
                #size-cells = <0>;

diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
index 36a0db44fd288004dd6f37e09b00da6f67047db1..565b2273d67b4b98078ea0803440c9f8b5ff0e7e 100644 (file)
--- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
@@ -80,7 +80,6 @@
        status = "okay";
        phy-handle = <&phy0>;
        phy-mode = "sgmii";
-       is-internal-pcspma;
        mdio: mdio {
                #address-cells = <1>;
                #size-cells = <0>;

diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
index 5a60b86a574ec04fda39ce6346ad70fb8ab7eab9..1a9729703556bc5badf96d7ccc63ad52a353f44f 100644 (file)
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
@@ -90,7 +90,6 @@
        status = "okay";
        phy-handle = <&phy0>;
        phy-mode = "sgmii"; /* DTG generates this properly  1512 */
-       is-internal-pcspma;
        mdio: mdio {
                #address-cells = <1>;
                #size-cells = <0>;

diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
index ce7c5eb6d34667dae6addbd324c6258e0914071d..6349a0e10877aa929d871197a17e8c066a928284 100644 (file)
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
@@ -195,7 +195,6 @@
        phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
        phy-handle = <&phy0>;
        phy-mode = "sgmii";
-       is-internal-pcspma;
        assigned-clock-rates = <250000000>;
 };
 

diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
index 0a0cbd2b69ae20fbf1aaedcd2337e68e8611faff..b0d737d3caf002be8d3f2301f0f34750157a6083 100644 (file)
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
@@ -216,7 +216,6 @@
        phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
        phy-handle = <&phy0>;
        phy-mode = "sgmii";
-       is-internal-pcspma;
        assigned-clock-rates = <250000000>;
 };
 

diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
index b626d1aacf58bd849de3199b162fee72f9fa9c45..7849f8c540bff5dadafc681aa1b6715064804b85 100644 (file)
--- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
+++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
@@ -117,7 +117,6 @@
        status = "okay";
        phy-handle = <&phy0>;
        phy-mode = "sgmii"; /* DTG generates this properly 1512 */
-       is-internal-pcspma;
        /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
        mdio: mdio {
                #address-cells = <1>;

diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts
index e0632883e4ece26c4e2440e642b7719d5fdc66a3..4768fac71d023bcead454f2ff3976e86b2238620 100644 (file)
--- a/arch/arm/dts/zynqmp-vpk120-revA.dts
+++ b/arch/arm/dts/zynqmp-vpk120-revA.dts
@@ -118,7 +118,6 @@
        status = "okay";
        phy-handle = <&phy0>;
        phy-mode = "sgmii"; /* DTG generates this properly 1512 */
-       is-internal-pcspma;
        /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
        mdio: mdio {
                #address-cells = <1>;

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index fe7d10844507a03f64265c0bcaa3ffa7fdb64178..461805ae53ff3926cceee35ac0fca3dda09a9f3e 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -228,7 +228,6 @@ struct zynq_gem_priv {
        struct clk tx_clk;
        struct clk pclk;
        u32 max_speed;
-       bool int_pcs;
        bool dma_64bit;
        u32 clk_en_info;
        struct reset_ctl_bulk resets;
@@ -504,8 +503,7 @@ static int zynq_gem_init(struct udevice *dev)
         * Set SGMII enable PCS selection only if internal PCS/PMA
         * core is used and interface is SGMII.
         */
-       if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
-           priv->int_pcs) {
+       if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
                nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
                            ZYNQ_GEM_NWCFG_PCS_SEL;
        }
@@ -529,8 +527,7 @@ static int zynq_gem_init(struct udevice *dev)
                writel(nwcfg, &regs->nwcfg);
 
 #ifdef CONFIG_ARM64
-       if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
-           priv->int_pcs) {
+       if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
                /*
                 * Disable AN for fixed link configuration, enable otherwise.
                 * Must be written after PCS_SEL is set in nwconfig,
@@ -992,8 +989,6 @@ static int zynq_gem_of_to_plat(struct udevice *dev)
                return -EINVAL;
        priv->interface = pdata->phy_interface;
 
-       priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
-
        priv->clk_en_info = dev_get_driver_data(dev);
 
        return 0;