]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
rockchip: add CONFIG_IRAM_BASE for all SoCs
authorKever Yang <kever.yang@rock-chips.com>
Mon, 22 Jul 2019 11:59:09 +0000 (19:59 +0800)
committerKever Yang <kever.yang@rock-chips.com>
Fri, 26 Jul 2019 09:30:26 +0000 (17:30 +0800)
Rockchip SoCs have internal sram for bootrom data area and for
sdram init program space. Introduce the base address in case
we need to use it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
include/configs/rk3128_common.h
include/configs/rk3188_common.h
include/configs/rk322x_common.h
include/configs/rk3288_common.h
include/configs/rk3328_common.h
include/configs/rk3368_common.h
include/configs/rk3399_common.h
include/configs/rv1108_common.h

index 20d62439fbbbd15449a8da58af9475bc8d6a2533..d12696d6b37fa0c57da76cb39da9f6037b73dbf3 100644 (file)
@@ -19,6 +19,8 @@
 #define CONFIG_SYS_ARCH_TIMER
 #define CONFIG_SYS_HZ_CLOCK            24000000
 
+#define CONFIG_IRAM_BASE               0x10080000
+
 #define CONFIG_SYS_INIT_SP_ADDR                0x60100000
 #define CONFIG_SYS_LOAD_ADDR           0x60800800
 
index ec90088309a956e68c945d5a9b822faf12cf0979..92524b06adc663b830cd1dd33ad454b45336ab82 100644 (file)
@@ -23,6 +23,7 @@
 
 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE  (0x8000 - 0x800)
 #define CONFIG_ROCKCHIP_CHIP_TAG       "RK31"
+#define CONFIG_IRAM_BASE       0x10080000
 
 /* spl size 32kb sram - 2kb bootrom */
 #define CONFIG_SPL_MAX_SIZE            (0x8000 - 0x800)
index cc086999441e946e420acc8394a3f4a3989f517d..9582cdfb645d727039e72144d0f1110b0e8c6327 100644 (file)
@@ -24,6 +24,7 @@
 
 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE  (28 << 10)
 #define CONFIG_ROCKCHIP_CHIP_TAG       "RK32"
+#define CONFIG_IRAM_BASE               0x10080000
 
 #define CONFIG_SYS_SDRAM_BASE          0x60000000
 #define SDRAM_BANK_SIZE                        (512UL << 20UL)
index 5c3b35ccba78f6cbaf2314a640eb62fba05629dc..da10e291399172575c8633c19bc9771612a9d3f1 100644 (file)
@@ -27,6 +27,8 @@
 #define CONFIG_SYS_LOAD_ADDR           0x00800800
 #define CONFIG_SPL_STACK               0xff718000
 
+#define CONFIG_IRAM_BASE               0xff700000
+
 /* RAW SD card / eMMC locations. */
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     (128 << 10)
 
index 3a8e37ef988eda99b78248c47fb755cfeaed4e08..1cf45bbb3e3075d4147cf0ce1904b812e20f497b 100644 (file)
@@ -8,6 +8,8 @@
 
 #include "rockchip-common.h"
 
+#define CONFIG_IRAM_BASE               0xff090000
+
 #define CONFIG_SYS_MALLOC_LEN          (32 << 20)
 #define CONFIG_SYS_CBSIZE              1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
index 1a859a7e430483c2275b392b7c8c31f4d9c941fb..340413dbbad3f82dd9c3b0a92a835f77eb22d3bc 100644 (file)
@@ -23,6 +23,8 @@
 #define CONFIG_ROCKCHIP_STIMER_BASE    0xff830020
 #define COUNTER_FREQUENCY              24000000
 
+#define CONFIG_IRAM_BASE               0xff8c0000
+
 #define CONFIG_SYS_INIT_SP_ADDR                0x00300000
 #define CONFIG_SYS_LOAD_ADDR           0x00280000
 
index 63eac19a4e7eaa6bec652d1ba9a95d11f65725b3..12ad60d4439f559375fd8d028eb5c0ad7cbec534 100644 (file)
@@ -15,6 +15,8 @@
 #define COUNTER_FREQUENCY               24000000
 #define CONFIG_ROCKCHIP_STIMER_BASE    0xff8680a0
 
+#define CONFIG_IRAM_BASE               0xff8c0000
+
 #define CONFIG_SYS_INIT_SP_ADDR                0x00300000
 #define CONFIG_SYS_LOAD_ADDR           0x00800800
 
index 6f61f015387982c99a21743f195d9e8b779d6caa..691aa51e9873c117b9e03efd09c5ab98790e8ff1 100644 (file)
@@ -8,6 +8,8 @@
 #include <asm/arch-rockchip/hardware.h>
 #include "rockchip-common.h"
 
+#define CONFIG_IRAM_BASE               0x10080000
+
 #define CONFIG_SYS_MALLOC_LEN          (32 << 20)
 #define CONFIG_SYS_CBSIZE              1024
 #define CONFIG_SKIP_LOWLEVEL_INIT