riscv: sifive: fu540: enable all cache ways from U-Boot proper

Add L2 cache node to enable all cache ways from U-Boot proper.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
index 043fb961a51e99abfe6e8a976f9ee20cea74d6f0..088205ef57e7698de573f3857397386a5ecb6d77 100644 (file)
--- a/arch/riscv/cpu/fu540/Makefile
+++ b/arch/riscv/cpu/fu540/Makefile
@@ -8,4 +8,5 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
+obj-y += cache.o
 endif

diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
new file mode 100644 (file)
index 0000000..9ee364b
--- /dev/null
+++ b/arch/riscv/cpu/fu540/cache.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+/* Register offsets */
+#define L2_CACHE_CONFIG        0x000
+#define L2_CACHE_ENABLE        0x008
+
+#define MASK_NUM_WAYS  GENMASK(15, 8)
+#define NUM_WAYS_SHIFT 8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cache_enable_ways(void)
+{
+       const void *blob = gd->fdt_blob;
+       int node = (-FDT_ERR_NOTFOUND);
+       fdt_addr_t base;
+       u32 config;
+       u32 ways;
+
+       volatile u32 *enable;
+
+       node = fdt_node_offset_by_compatible(blob, -1,
+                                            "sifive,fu540-c000-ccache");
+
+       if (node < 0)
+               return node;
+
+       base = fdtdec_get_addr(blob, node, "reg");
+       if (base == FDT_ADDR_T_NONE)
+               return FDT_ADDR_T_NONE;
+
+       config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
+       ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+
+       enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
+
+       /* memory barrier */
+       mb();
+       (*enable) = ways - 1;
+       /* memory barrier */
+       mb();
+       return 0;
+}

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index 35c153d8515f2e28ba24b59016f0c5a6c2ff0541..afdb4f4402ecf87caa7eca2d51962dae8ff1d0f0 100644 (file)
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -87,3 +87,7 @@
        assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
        assigned-clock-rates = <125000000>;
 };
+
+&l2cache {
+       status = "okay";
+};

diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h
new file mode 100644 (file)
index 0000000..135a17c
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/cache.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 SiFive, Inc.
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _CACHE_SIFIVE_H
+#define _CACHE_SIFIVE_H
+
+int cache_enable_ways(void);
+
+#endif /* _CACHE_SIFIVE_H */

diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index fa705dea71dfcf6024c0b2fcac6e82c20eac2927..27ff52f90355ccd8262811ba4de98b41653eccd9 100644 (file)
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <misc.h>
 #include <spl.h>
+#include <asm/arch/cache.h>
 
 /*
  * This define is a value used for error/unknown serial.
@@ -114,7 +115,14 @@ int misc_init_r(void)
 
 int board_init(void)
 {
-       /* For now nothing to do here. */
+       int ret;
+
+       /* enable all cache ways */
+       ret = cache_enable_ways();
+       if (ret) {
+               debug("%s: could not enable cache ways\n", __func__);
+               return ret;
+       }
 
        return 0;
 }