armv8: K3: j721e: Add custom MMU support

The A72 U-Boot code loads and boots a number of remote processors
including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various
Main R5FSS Cores. Change the memory attributes for the DDR regions used
by the remote processors so that the cores can see and execute the
proper code.

A separate table based on the current AM65x table is added for J721E SoCs,
since the number of remote processors and their DDR usage will be different
between the two SoC families.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index a75ba1ffdba01f357622a202fa8be464227e5e8d..82778d2197aabf5947a537ae49782ba997a0067a 100644 (file)
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -12,6 +12,7 @@
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
 
+#ifdef CONFIG_SOC_K3_AM6
 /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
 #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
 
@@ -43,3 +44,57 @@ struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
 };
 
 struct mm_region *mem_map = am654_mem_map;
+#endif /* CONFIG_SOC_K3_AM6 */
+
+#ifdef CONFIG_SOC_K3_J721E
+/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
+
+/* ToDo: Add 64bit IO */
+struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
+       {
+               .virt = 0x0UL,
+               .phys = 0x0UL,
+               .size = 0x80000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               .virt = 0x80000000UL,
+               .phys = 0x80000000UL,
+               .size = 0x20000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               .virt = 0xa0000000UL,
+               .phys = 0xa0000000UL,
+               .size = 0x0bc00000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+                        PTE_BLOCK_NON_SHARE
+       }, {
+               .virt = 0xabc00000UL,
+               .phys = 0xabc00000UL,
+               .size = 0x54400000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               .virt = 0x880000000UL,
+               .phys = 0x880000000UL,
+               .size = 0x80000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               .virt = 0x500000000UL,
+               .phys = 0x500000000UL,
+               .size = 0x400000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* List terminator */
+               0,
+       }
+};
+
+struct mm_region *mem_map = j721e_mem_map;
+#endif /* CONFIG_SOC_K3_J721E */