ata: ahci: Don't forget to clear upper address regs.

In 32bits mode upper bits need to be set to 0, otherwise controller will
try to DMA into not existing memory and stops with error.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Oleksandr Rybalko <ray@ddteam.net>

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 9a08575053dd5a25d2d2b5c0f85387c46a3ab606..21a89eba5af5b1dab0fa766e3c961b1d7754c238 100644 (file)
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -548,6 +548,7 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
 {
        struct ahci_ioports *pp = &(uc_priv->port[port]);
        void __iomem *port_mmio = pp->port_mmio;
+       u64 dma_addr;
        u32 port_status;
        void __iomem *mem;
 
@@ -593,10 +594,12 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
        pp->cmd_tbl_sg =
                        (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
 
-       writel_with_flush((unsigned long)pp->cmd_slot,
-                         port_mmio + PORT_LST_ADDR);
-
-       writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
+       dma_addr = (ulong)pp->cmd_slot;
+       writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
+       writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
+       dma_addr = (ulong)pp->rx_fis;
+       writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
+       writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
 
 #ifdef CONFIG_SUNXI_AHCI
        sunxi_dma_init(port_mmio);