--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Peter Robinson <pbrobinson at gmail.com>
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+ };
+
+ config {
+ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */
+ };
+};
+
+&rng {
+ status = "okay";
+};
+
+&sdhci {
+ max-frequency = <25000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ max-frequency = <20000000>;
+ u-boot,dm-pre-reloc;
+};
with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port,
1920*1080 screen and all the usual laptop features.
+config TARGET_PINEPHONE_PRO_RK3399
+ bool "PinePhone Pro"
+ help
+ PinePhone Pro is a phone based on a variant of the Rockchip
+ rk3399 SoC with 4Gb RAM, onboard eMMC, USB-C, headphone jack,
+ 720x1440 screen and a Quectel 4G/LTE modem.
+
config TARGET_PUMA_RK3399
bool "Theobroma Systems RK3399-Q7 (Puma)"
help
source "board/firefly/roc-pc-rk3399/Kconfig"
source "board/google/gru/Kconfig"
source "board/pine64/pinebook-pro-rk3399/Kconfig"
+source "board/pine64/pinephone-pro-rk3399/Kconfig"
source "board/pine64/rockpro64_rk3399/Kconfig"
source "board/rockchip/evb_rk3399/Kconfig"
source "board/theobroma-systems/puma_rk3399/Kconfig"
--- /dev/null
+if TARGET_PINEPHONE_PRO_RK3399
+
+config SYS_BOARD
+ default "pinephone-pro-rk3399"
+
+config SYS_VENDOR
+ default "pine64"
+
+config SYS_CONFIG_NAME
+ default "pinephone-pro-rk3399"
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+
+endif
--- /dev/null
+PINEPHONE_PRO
+M: Peter Robinson <pbrobinson@gmail.com>
+S: Maintained
+F: board/pine64/rk3399-pinephone-pro/
+F: include/configs/rk3399-pinephone-pro.h
+F: arch/arm/dts/rk3399-pinephone-pro.dts
+F: arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
+F: configs/pinephone-pro-rk3399_defconfig
--- /dev/null
+obj-y += pinephone-pro-rk3399.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2022 Peter Robinson <pbrobinson at gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/misc.h>
+#include <power/regulator.h>
+
+#define GRF_IO_VSEL_BT565_SHIFT 0
+#define PMUGRF_CON0_VSEL_SHIFT 8
+
+#ifndef CONFIG_SPL_BUILD
+int board_early_init_f(void)
+{
+ struct udevice *regulator;
+ int ret;
+
+ ret = regulator_get_by_platname("vcc5v0_usb", ®ulator);
+ if (ret) {
+ pr_debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret);
+ goto out;
+ }
+
+ ret = regulator_set_enable(regulator, true);
+ if (ret)
+ pr_debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret);
+
+out:
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+static void setup_iodomain(void)
+{
+ struct rk3399_grf_regs *grf =
+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ struct rk3399_pmugrf_regs *pmugrf =
+ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+
+ /* BT565 is in 1.8v domain */
+ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
+
+ /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
+ rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
+}
+
+int misc_init_r(void)
+{
+ const u32 cpuid_offset = 0x7;
+ const u32 cpuid_length = 0x10;
+ u8 cpuid[cpuid_length];
+ int ret;
+
+ setup_iodomain();
+
+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+ if (ret)
+ return ret;
+
+ ret = rockchip_cpuid_set(cpuid, cpuid_length);
+ if (ret)
+ return ret;
+
+ return ret;
+}
+#endif
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00200000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x8000
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro"
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_PINEPHONE_PRO_RK3399=y
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_BOOTDELAY=3
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb"
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x400000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x400000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_DM_PMIC_FAN53555=y
+CONFIG_DM_REGULATOR_FAN53555=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_EDP=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd
+ * Copyright (C) 2022 Peter Robinson <pbrobinson at gmail.com>
+ */
+
+#ifndef __PINEPHONE_PRO_RK3399_H
+#define __PINEPHONE_PRO_RK3399_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3399_common.h>
+
+#define SDRAM_BANK_SIZE (2UL << 30)
+
+#endif