ARM: Introduce erratum workaround for 430973

430973: Stale prediction on replaced inter working branch causes
	Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/README b/README
index c3226386cfdb70a1223c4d431f8c96e61a22fadf..360f2a9f70b866bb83e8bb026289556d8e6657c7 100644 (file)
--- a/README
+++ b/README
@@ -693,6 +693,7 @@ The following options need to be configured:
                NOTE: The following can be machine specific errata. These
                do have ability to provide rudimentary version and machine
                specific checks, but expect no product checks.
+               CONFIG_ARM_ERRATA_430973
                CONFIG_ARM_ERRATA_454179
                CONFIG_ARM_ERRATA_798870
 

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 8483687879ed70054deb33cc4f56e22780ac1544..41fb24cf321b25ed9ff3d6c4cdebea28e380fa0e 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -200,6 +200,19 @@ skip_errata_798870:
        pop     {r1-r5}                 @ Restore the cpu info - fall through
 
 skip_errata_454179:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_430973
+       cmp     r2, #0x21               @ Only on < r2p1
+       bge     skip_errata_430973
+
+       mrc     p15, 0, r0, c1, c0, 1   @ Read ACR
+       orr     r0, r0, #(0x1 << 6)     @ Set IBE bit
+       push    {r1-r5}                 @ Save the cpu info registers
+       bl      v7_arch_cp15_set_acr
+       pop     {r1-r5}                 @ Restore the cpu info - fall through
+
+skip_errata_430973:
 #endif
 
        mov     pc, r5                  @ back to my caller