imx8mp: DDR performance tunning

1. set SCHED.rdwr_idle_gap=0
2. set SCHED.pageclose=1

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Jian Li <jian.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c
index 6b17b3f1413e359b2375856e1378ecd5b957d33f..75d6b530d25cbd024dc9ee70795e3d14dc6c87ac 100644 (file)
--- a/board/freescale/imx8mp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -52,7 +52,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d400214, 0x7070707 },
        { 0x3d400218, 0x68070707 },
        { 0x3d40021c, 0xf08 },
-       { 0x3d400250, 0x29001701 },
+       { 0x3d400250, 0x00001705 },
        { 0x3d400254, 0x2c },
        { 0x3d40025c, 0x4000030 },
        { 0x3d400264, 0x900093e7 },