rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF support

Add dummy support for the CLK_PCIEPHY2_REF clock.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 6bdd96f35b5c9453f8db0058ecdd2d3ace66771d..0df82f597152b27f60327185c9bad2255578dbb3 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -427,6 +427,7 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate)
                break;
        case CLK_PCIEPHY0_REF:
        case CLK_PCIEPHY1_REF:
+       case CLK_PCIEPHY2_REF:
                return 0;
        default:
                return -ENOENT;