arm: dts: MediaTek: fix clock order for timer0 node of mt7629.dtsi

The timer0 node has its two clocks written in reversed order. The timer0
is used as the tick timer which causes a problem that the time a delay
function used is 4 times longer.

This patch reverses these two clocks to solve this issue.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index c87115e0fe4ce382fbfce1077f51df627c465173..ecbd29d7ae430106e1f792ddaa9105a4f5e1c10c 100644 (file)
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -82,8 +82,8 @@
                compatible = "mediatek,timer";
                reg = <0x10004000 0x80>;
                interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
-               clocks = <&topckgen CLK_TOP_10M_SEL>,
-                        <&topckgen CLK_TOP_CLKXTAL_D4>;
+               clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
+                        <&topckgen CLK_TOP_10M_SEL>;
                clock-names = "mux", "src";
                u-boot,dm-pre-reloc;
        };