rockchip: clk: Add mention of four new clocks

These clocks are needed to get MMC running. We don't actually support
setting them yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 198914b0676685fd1b1c98ec64fa1634c08a3663..cab2bd994331dfa1f0afc053d08c97a2b4dc9a21 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -925,7 +925,13 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
        case SCLK_SARADC:
                rate = rk3399_saradc_get_clk(priv->cru);
                break;
+       case ACLK_VIO:
+       case ACLK_HDCP:
+       case ACLK_GIC_PRE:
+       case PCLK_DDR:
+               break;
        default:
+               log_debug("Unknown clock %lu\n", clk->id);
                return -ENOENT;
        }
 
@@ -993,7 +999,13 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
        case SCLK_SARADC:
                ret = rk3399_saradc_set_clk(priv->cru, rate);
                break;
+       case ACLK_VIO:
+       case ACLK_HDCP:
+       case ACLK_GIC_PRE:
+       case PCLK_DDR:
+               return 0;
        default:
+               log_debug("Unknown clock %lu\n", clk->id);
                return -ENOENT;
        }