ARM: dts: add hifsys reset for MediaTek SoCs

This adds missing hifsys reset parts in header files.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>

diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 448d1d73810e549bc7c02fb6cadc7d759b315187..64079c61bfb47f972c869b3b3a1c743d2c0ceea1 100644 (file)
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -248,6 +248,13 @@
                status = "disabled";
        };
 
+       hifsys: syscon@1a000000 {
+               compatible = "mediatek,mt7623-hifsys", "syscon";
+               reg = <0x1a000000 0x1000>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+       };
+
        ethsys: syscon@1b000000 {
                compatible = "mediatek,mt7623-ethsys", "syscon";
                reg = <0x1b000000 0x1000>;

diff --git a/include/dt-bindings/reset/mtk-reset.h b/include/dt-bindings/reset/mtk-reset.h
index 5f0a74f280c7961dbb82255bc42d3fb8bc5cad11..78fcdab009dab3c6da1f13562a2d73c1010f705b 100644 (file)
--- a/include/dt-bindings/reset/mtk-reset.h
+++ b/include/dt-bindings/reset/mtk-reset.h
@@ -15,4 +15,13 @@
 #define ETHSYS_MCM_RST                 2
 #define ETHSYS_SYS_RST                 0
 
+/* HIFSYS resets */
+#define HIFSYS_PCIE2_RST               26
+#define HIFSYS_PCIE1_RST               25
+#define HIFSYS_PCIE0_RST               24
+#define HIFSYS_UPHY1_RST               22
+#define HIFSYS_UPHY0_RST               21
+#define HIFSYS_UHOST1_RST              4
+#define HIFSYS_UHOST0_RST              3
+
 #endif /* _DT_BINDINGS_MTK_RESET_H_ */