]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
imx: imx8mm_icore: Enable SPL_DM_SERIAL
authorPeng Fan <peng.fan@nxp.com>
Sat, 11 Jun 2022 12:20:57 +0000 (20:20 +0800)
committerStefano Babic <sbabic@denx.de>
Tue, 14 Jun 2022 19:33:13 +0000 (21:33 +0200)
Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
board/engicam/imx8mm/spl.c
configs/imx8mm-icore-mx8mm-ctouch2_defconfig
configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
include/configs/imx8mm_icore_mx8mm.h

index f9be769ec59959457e5d4b45c993fd274aaaa74b..f75f2dc634c758af2b48cbee04558bf018cd9a24 100644 (file)
@@ -54,19 +54,11 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
-#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
 #define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
 
-static iomux_v3_cfg_t const uart_pads[] = {
-       IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-       IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 int board_early_init_f(void)
 {
-       imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
-       return 0;
+       return 0;
 }
 
 void board_init_f(ulong dummy)
@@ -81,8 +73,6 @@ void board_init_f(ulong dummy)
 
        timer_init();
 
-       preloader_console_init();
-
        /* Clear the BSS. */
        memset(__bss_start, 0, __bss_end - __bss_start);
 
@@ -92,6 +82,8 @@ void board_init_f(ulong dummy)
                hang();
        }
 
+       preloader_console_init();
+
        enable_tzc380();
 
        /* DDR initialization */
index c95ff3e74fb409769473a29c7a32cba6d1b2700a..b831adb1121d7c11dd1054618158cbd1f24fc29b 100644 (file)
@@ -87,7 +87,6 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_CONS_INDEX=2
 CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
index 62d2394996907eb863f5dbc7c2544ecf2dbb7918..614bacbfbf2056f388b9e5e7ea796a1b75c83f12 100644 (file)
@@ -87,7 +87,6 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_CONS_INDEX=2
 CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
index e6642936cba0a97fcb5de4e800a6c3626c7ed900..a3db85004e2057a2ae152e3efac4cad7e9fbbf4e 100644 (file)
@@ -54,9 +54,6 @@
 #define PHYS_SDRAM_SIZE                        SZ_2G /* 2GB DDR */
 #define CONFIG_SYS_BOOTM_LEN           SZ_256M
 
-/* UART */
-#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(2)
-
 /* USDHC */
 #define CONFIG_SYS_FSL_USDHC_NUM       2
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0