phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initialization

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
Root Complex mode.

Same change was included in TF-A project:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index 06822d1d12e0829d9f8ae8af2af579faffb16a9d..504f4b2bb182f76fac77cff6b3ba264c3f97933a 100644 (file)
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -200,7 +200,7 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
         * 6. Enable the output of 100M/125M/500M clock
         */
        reg_set16(phy_addr(PCIE, MISC_REG0),
-                 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF);
+                 0xA00D | rb_clk500m_en | rb_txdclk_2x_sel | rb_clk100m_125m_en, 0xFFFF);
 
        /*
         * 7. Enable TX

diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h
index 8748c6c84ae6deee028b683e2ef5e06152ba58ac..23c8ffbff44d9becb54c3e350941152c2aaacc03 100644 (file)
--- a/drivers/phy/marvell/comphy_a3700.h
+++ b/drivers/phy/marvell/comphy_a3700.h
@@ -120,6 +120,7 @@ static inline void __iomem *phy_addr(enum phy_unit unit, u32 addr)
 
 #define MISC_REG0                      0x4f
 #define rb_clk100m_125m_en             BIT(4)
+#define rb_txdclk_2x_sel               BIT(6)
 #define rb_clk500m_en                  BIT(7)
 #define rb_ref_clk_sel                 BIT(10)