rockchip: add common spl board file

The common spl board file handles board_init_f() in SPL,
and with board_early_init_f() and arch_cpu_init() callback,
other operateion after board_init_f() should go to board specific
spl_board_init().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 17f31e89f35818fe0621cd40f49835d119e273ca..ac86532c8829a04f21391fe79db33b7258de6fbf 100644 (file)
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -227,6 +227,14 @@ config TPL_ROCKCHIP_BACK_TO_BROM
           SPL will return to the boot rom, which will then load the U-Boot
           binary to keep going on.
 
+config SPL_ROCKCHIP_COMMON_BOARD
+       bool "Rockchip SPL common board file"
+       depends on SPL
+       help
+         Rockchip SoCs have similar boot process, SPL is mainly in charge of
+         load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
+         no TPL for the board.
+
 config TPL_ROCKCHIP_COMMON_BOARD
        bool ""
        depends on TPL

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index a12b8d4434ec3e360c327a1d91cd6b01d4ccf4e8..b831ec6f2b54ebaa6242d07a2fb79c0b0c66152a 100644 (file)
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -7,6 +7,7 @@
 # inaccessible/protected memory (and the bootrom-helper assumes that
 # the stack-pointer is valid before switching to the U-Boot stack).
 obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
+obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o
 obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
 obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o
 

diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
new file mode 100644 (file)
index 0000000..33137cc
--- /dev/null
+++ b/arch/arm/mach-rockchip/spl.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/sdram.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_return_to_bootrom(void)
+{
+       back_to_bootrom(BROM_BOOT_NEXTSTAGE);
+}
+
+__weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+};
+
+const char *board_spl_was_booted_from(void)
+{
+       u32  bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
+       const char *bootdevice_ofpath = NULL;
+
+       if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
+               bootdevice_ofpath = boot_devices[bootdevice_brom_id];
+
+       if (bootdevice_ofpath)
+               debug("%s: brom_bootdevice_id %x maps to '%s'\n",
+                     __func__, bootdevice_brom_id, bootdevice_ofpath);
+       else
+               debug("%s: failed to resolve brom_bootdevice_id %x\n",
+                     __func__, bootdevice_brom_id);
+
+       return bootdevice_ofpath;
+}
+
+u32 spl_boot_device(void)
+{
+       u32 boot_device = BOOT_DEVICE_MMC1;
+
+#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
+               defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
+               defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
+       return BOOT_DEVICE_SPI;
+#endif
+       if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
+               return BOOT_DEVICE_BOOTROM;
+
+       return boot_device;
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+       return MMCSD_MODE_RAW;
+}
+
+#if !defined(CONFIG_ROCKCHIP_RK3188)
+#define TIMER_LOAD_COUNT_L     0x00
+#define TIMER_LOAD_COUNT_H     0x04
+#define TIMER_CONTROL_REG      0x10
+#define TIMER_EN       0x1
+#define        TIMER_FMODE     BIT(0)
+#define        TIMER_RMODE     BIT(1)
+
+__weak void rockchip_stimer_init(void)
+{
+       /* If Timer already enabled, don't re-init it */
+       u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+
+       if (reg & TIMER_EN)
+               return;
+#ifndef CONFIG_ARM64
+       asm volatile("mcr p15, 0, %0, c14, c0, 0"
+                    : : "r"(COUNTER_FREQUENCY));
+#endif
+       writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+       writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
+       writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
+       writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
+              TIMER_CONTROL_REG);
+}
+#endif
+
+__weak int board_early_init_f(void)
+{
+       return 0;
+}
+
+__weak int arch_cpu_init(void)
+{
+       return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+       int ret;
+#if !defined(CONFIG_SUPPORT_TPL) || defined(CONFIG_SPL_OS_BOOT)
+       struct udevice *dev;
+#endif
+
+#ifdef CONFIG_DEBUG_UART
+       /*
+        * Debug UART can be used from here if required:
+        *
+        * debug_uart_init();
+        * printch('a');
+        * printhex8(0x1234);
+        * printascii("string");
+        */
+       debug_uart_init();
+       debug("\nspl:debug uart enabled in %s\n", __func__);
+#endif
+
+       board_early_init_f();
+
+       ret = spl_early_init();
+       if (ret) {
+               printf("spl_early_init() failed: %d\n", ret);
+               hang();
+       }
+       arch_cpu_init();
+#if !defined(CONFIG_SUPPORT_TPL) || defined(CONFIG_SPL_OS_BOOT)
+       debug("\nspl:init dram\n");
+       ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+       if (ret) {
+               printf("DRAM init failed: %d\n", ret);
+               return;
+       }
+#endif
+#if !defined(CONFIG_ROCKCHIP_RK3188)
+       rockchip_stimer_init();
+#endif
+#ifdef CONFIG_SYS_ARCH_TIMER
+       /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
+       timer_init();
+#endif
+       preloader_console_init();
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+       /* Just empty function now - can't decide what to choose */
+       debug("%s: %s\n", __func__, name);
+
+       return 0;
+}
+#endif