clk: renesas: Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.1.7

Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index c1283d2614c7a89bb898476ae8f5fe28602d3efe..f2dce5d8853f89651a553cdf5906230b389c9870 100644 (file)
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -2,12 +2,12 @@
 /*
  * r8a774c0 Clock Pulse Generator / Module Standby and Software Reset
  *
- * Copyright (C) 2020 Renesas Electronics Corp.
+ * Copyright (C) 2018 Renesas Electronics Corp.
  *
  * Based on r8a77990-cpg-mssr.c
  *
  * Copyright (C) 2015 Glider bvba
- * Copyright (C) 2020 Renesas Electronics Corp.
+ * Copyright (C) 2015 Renesas Electronics Corp.
  */
 
 #include <common.h>
@@ -77,11 +77,6 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = {
 
        DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
 
-       DEF_BASE("rpc",         R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
-                CLK_RPCSRC),
-       DEF_BASE("rpcd2",       R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
-                R8A774C0_CLK_RPC),
-
        DEF_DIV6_RO(".r",      CLK_RINT,           CLK_EXTAL, CPG_RCKCR, 32),
 
        DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),
@@ -108,9 +103,15 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = {
        DEF_FIXED("s3d2",      R8A774C0_CLK_S3D2,  CLK_S3,         2, 1),
        DEF_FIXED("s3d4",      R8A774C0_CLK_S3D4,  CLK_S3,         4, 1),
 
-       DEF_GEN3_SD("sd0",     R8A774C0_CLK_SD0,   CLK_SDSRC,     0x0074),
-       DEF_GEN3_SD("sd1",     R8A774C0_CLK_SD1,   CLK_SDSRC,     0x0078),
-       DEF_GEN3_SD("sd3",     R8A774C0_CLK_SD3,   CLK_SDSRC,     0x026c),
+       DEF_BASE("rpc",        R8A774C0_CLK_RPC,   CLK_TYPE_GEN3_RPC,   CLK_RPCSRC),
+       DEF_BASE("rpcd2",      R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774C0_CLK_RPC),
+
+       DEF_GEN3_SDH("sd0h",   R8A774C0_CLK_SD0H, CLK_SDSRC,         0x0074),
+       DEF_GEN3_SDH("sd1h",   R8A774C0_CLK_SD1H, CLK_SDSRC,         0x0078),
+       DEF_GEN3_SDH("sd3h",   R8A774C0_CLK_SD3H, CLK_SDSRC,         0x026c),
+       DEF_GEN3_SD("sd0",     R8A774C0_CLK_SD0,  R8A774C0_CLK_SD0H, 0x0074),
+       DEF_GEN3_SD("sd1",     R8A774C0_CLK_SD1,  R8A774C0_CLK_SD1H, 0x0078),
+       DEF_GEN3_SD("sd3",     R8A774C0_CLK_SD3,  R8A774C0_CLK_SD3H, 0x026c),
 
        DEF_FIXED("cl",        R8A774C0_CLK_CL,    CLK_PLL1,      48, 1),
        DEF_FIXED("cp",        R8A774C0_CLK_CP,    CLK_EXTAL,      2, 1),
@@ -210,7 +211,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] = {
        DEF_MOD("rpc-if",                917,   R8A774C0_CLK_RPCD2),
        DEF_MOD("i2c6",                  918,   R8A774C0_CLK_S3D2),
        DEF_MOD("i2c5",                  919,   R8A774C0_CLK_S3D2),
-       DEF_MOD("i2c-dvfs",              926,   R8A774C0_CLK_CP),
+       DEF_MOD("iic-pmic",              926,   R8A774C0_CLK_CP),
        DEF_MOD("i2c4",                  927,   R8A774C0_CLK_S3D2),
        DEF_MOD("i2c3",                  928,   R8A774C0_CLK_S3D2),
        DEF_MOD("i2c2",                  929,   R8A774C0_CLK_S3D2),