board: stm32mp1: correct the property name for eth

Use the correct name for STMicroelectronics phys config properties,
replace '_' by '-':
  "st,eth_clk_sel" => "st,eth-clk-sel"
  "st,eth-ref-clk-sel" => st,eth-clk-sel"

These property name are aligned with the upstreamed Linux kernel binding:
 linux/Documentation/devicetree/bindings/net/stm32-dwmac.yaml

See Linux kernel commit "dt-bindings: net: stmmac: add phys config
properties" merged in v5.1-rc1.

This patch allow to reuse the kernel device tree directly in U-Boot.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index ac1af718d4affef10c307703dbbb503cb3271ccc..d7c1857c16855d6b2d6bf73378a5bb7cd19d8ebf 100644 (file)
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -660,11 +660,11 @@ int board_interface_eth_init(struct udevice *dev,
        bool eth_ref_clk_sel_reg = false;
 
        /* Gigabit Ethernet 125MHz clock selection. */
-       eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
+       eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
 
        /* Ethernet 50Mhz RMII clock selection */
        eth_ref_clk_sel_reg =
-               dev_read_bool(dev, "st,eth_ref_clk_sel");
+               dev_read_bool(dev, "st,eth-ref-clk-sel");
 
        syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
 

diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 261ec15e1b0ad95c225abdc7bbe13666c8fe9118..18b8870269fee0f217b073743ff317e161314475 100644 (file)
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -733,11 +733,11 @@ int board_interface_eth_init(struct udevice *dev,
        bool eth_ref_clk_sel_reg = false;
 
        /* Gigabit Ethernet 125MHz clock selection. */
-       eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
+       eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel");
 
        /* Ethernet 50Mhz RMII clock selection */
        eth_ref_clk_sel_reg =
-               dev_read_bool(dev, "st,eth_ref_clk_sel");
+               dev_read_bool(dev, "st,eth-ref-clk-sel");
 
        syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);