I2C_READ
- Code that returns TRUE if the I2C data line is high,
- FALSE if it is low.
+ Code that returns true if the I2C data line is high,
+ false if it is low.
eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
I2C_SDA(bit)
- If <bit> is TRUE, sets the I2C data line high. If it
- is FALSE, it clears it (low).
+ If <bit> is true, sets the I2C data line high. If it
+ is false, it clears it (low).
eg: #define I2C_SDA(bit) \
if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
I2C_SCL(bit)
- If <bit> is TRUE, sets the I2C clock line high. If it
- is FALSE, it clears it (low).
+ If <bit> is true, sets the I2C clock line high. If it
+ is false, it clears it (low).
eg: #define I2C_SCL(bit) \
if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
#include <asm/arch/spr_misc.h>
#include <asm/arch/spr_defs.h>
-#define FALSE 0
-#define TRUE (!FALSE)
-
static void sel_1v8(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
/*
* xxx_boot_selected:
*
- * return TRUE if the particular booting option is selected
- * return FALSE otherwise
+ * return true if the particular booting option is selected
+ * return false otherwise
*/
static u32 read_bootstrap(void)
{
/* Check whether SNOR boot is selected */
if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
CONFIG_SPEAR_ONLYSNORBOOT)
- return TRUE;
+ return true;
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND8BOOT)
- return TRUE;
+ return true;
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND16BOOT)
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
int nand_boot_selected(void)
/* Check whether NAND boot is selected */
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND8BOOT)
- return TRUE;
+ return true;
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND16BOOT)
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
int pnor_boot_selected(void)
{
/* Parallel NOR boot is not selected in any SPEAr600 revision */
- return FALSE;
+ return false;
}
int usb_boot_selected(void)
if (USB_BOOT_SUPPORTED) {
/* Check whether USB boot is selected */
if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
int tftp_boot_selected(void)
{
/* TFTP boot is not selected in any SPEAr600 revision */
- return FALSE;
+ return false;
}
int uart_boot_selected(void)
{
/* UART boot is not selected in any SPEAr600 revision */
- return FALSE;
+ return false;
}
int spi_boot_selected(void)
{
/* SPI boot is not selected in any SPEAr600 revision */
- return FALSE;
+ return false;
}
int i2c_boot_selected(void)
{
/* I2C boot is not selected in any SPEAr600 revision */
- return FALSE;
+ return false;
}
int mmc_boot_selected(void)
{
- return FALSE;
+ return false;
}
void plat_late_init(void)
/*
* All the supported booting devices are listed here. Each of
* the booting type supported by the platform would define the
- * macro xxx_BOOT_SUPPORTED to TRUE.
+ * macro xxx_BOOT_SUPPORTED to true.
*/
if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {
typedef unsigned short __kernel_old_uid_t;
typedef unsigned short __kernel_old_gid_t;
-#define BOOL_WAS_DEFINED
-typedef enum { false = 0, true = 1 } bool;
-
#ifdef __GNUC__
typedef long long __kernel_loff_t;
#endif
sr = get_sr ();
set_sr (sr | 0x0700);
- return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */
+ return ((sr & 0x0700) == 0); /* return true, if interrupts were enabled before */
}
void int_handler (struct pt_regs *fp)
/*
* disable interrupts
- * Return TRUE if GIE is enabled before we disable it.
+ * Return true if GIE is enabled before we disable it.
*/
int disable_interrupts(void)
{
size_t arglen;
#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
- int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */
+ int need_serdes_a001; /* true == need work-around for SERDES A001 */
#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
char buffer[HWCONFIG_BUFFER_SIZE];
#define NUMMEMTESTS 8
#define NUMMEMWORDS 8
#define MAXBXCR 4
-#define TRUE 1
-#define FALSE 0
/*
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
unsigned char num_of_bytes;
unsigned char total_size;
- dimm_found = FALSE;
+ dimm_found = false;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
num_of_bytes = 0;
total_size = 0;
total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
if ((num_of_bytes != 0) && (total_size != 0)) {
- dimm_populated[dimm_num] = TRUE;
- dimm_found = TRUE;
+ dimm_populated[dimm_num] = true;
+ dimm_found = true;
debug("DIMM slot %lu: populated\n", dimm_num);
} else {
- dimm_populated[dimm_num] = FALSE;
+ dimm_populated[dimm_num] = false;
debug("DIMM slot %lu: Not populated\n", dimm_num);
}
}
- if (dimm_found == FALSE) {
+ if (dimm_found == false) {
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
spd_ddr_init_hang ();
}
unsigned char dimm_type;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
+ if (dimm_populated[dimm_num] == true) {
dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
switch (dimm_type) {
case 7:
unsigned long voltage_type;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
+ if (dimm_populated[dimm_num] == true) {
voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
if (voltage_type != 0x04) {
printf("ERROR: DIMM %lu with unsupported voltage level.\n",
/*
* FIXME: assume the DDR SDRAMs in both banks are the same
*/
- ecc_enabled = TRUE;
+ ecc_enabled = true;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
+ if (dimm_populated[dimm_num] == true) {
ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
if (ecc != 0x02) {
- ecc_enabled = FALSE;
+ ecc_enabled = false;
}
/*
/*
* program Memory Data Error Checking
*/
- if (ecc_enabled == TRUE) {
+ if (ecc_enabled == true) {
cfg0 |= SDRAM_CFG0_MCHK_GEN;
} else {
cfg0 |= SDRAM_CFG0_MCHK_NON;
bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
+ if (dimm_populated[dimm_num] == true) {
refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
switch (refresh_rate_type) {
case 0x00:
t_rp_ns = 0;
t_rcd_ns = 0;
t_ras_ns = 0;
- cas_2_0_available = TRUE;
- cas_2_5_available = TRUE;
- cas_3_0_available = TRUE;
+ cas_2_0_available = true;
+ cas_2_5_available = true;
+ cas_3_0_available = true;
tcyc_2_0_ns_x_10 = 0;
tcyc_2_5_ns_x_10 = 0;
tcyc_3_0_ns_x_10 = 0;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
+ if (dimm_populated[dimm_num] == true) {
wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
if (cas_index != 0) {
cas_index++;
}
- cas_3_0_available = FALSE;
+ cas_3_0_available = false;
}
if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
if (cas_index != 0) {
cas_index++;
}
- cas_2_5_available = FALSE;
+ cas_2_5_available = false;
}
if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
if (cas_index != 0) {
cas_index++;
}
- cas_2_0_available = FALSE;
+ cas_2_0_available = false;
}
break;
/*
* Program SD_CASL field
*/
- if ((cas_2_0_available == TRUE) &&
+ if ((cas_2_0_available == true) &&
(bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
- } else if ((cas_2_5_available == TRUE) &&
+ } else if ((cas_2_5_available == true) &&
(bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
- } else if ((cas_3_0_available == TRUE) &&
+ } else if ((cas_3_0_available == true) &&
(bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
} else {
current_fail_length = 0;
current_start = 0;
rdclt_offset = 0;
- window_found = FALSE;
- fail_found = FALSE;
- pass_found = FALSE;
+ window_found = false;
+ fail_found = false;
+ pass_found = false;
debug("Starting memory test ");
for (k = 0; k < NUMHALFCYCLES; k++) {
mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
if (short_mem_test()) {
- if (fail_found == TRUE) {
- pass_found = TRUE;
+ if (fail_found == true) {
+ pass_found = true;
if (current_pass_length == 0) {
current_start = rdclt_offset + rdclt;
}
current_fail_length++;
if (current_fail_length >= (dly_val>>2)) {
- if (fail_found == FALSE) {
- fail_found = TRUE;
- } else if (pass_found == TRUE) {
- window_found = TRUE;
+ if (fail_found == false) {
+ fail_found = true;
+ } else if (pass_found == true) {
+ window_found = true;
break;
}
}
}
debug(".");
- if (window_found == TRUE) {
+ if (window_found == true)
break;
- }
tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
rdclt_offset += dly_val;
/*
* make sure we find the window
*/
- if (window_found == FALSE) {
+ if (window_found == false) {
printf("ERROR: Cannot determine a common read delay.\n");
spd_ddr_init_hang ();
}
bank_base_addr = CONFIG_SYS_SDRAM_BASE;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
+ if (dimm_populated[dimm_num] == true) {
num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
/*-----------------------------------------------------------------------------+
* Defines
*-----------------------------------------------------------------------------*/
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
#define SDRAM_DDR1 1
#define SDRAM_DDR2 2
#define SDRAM_NONE 0
unsigned char num_of_bytes;
unsigned char total_size;
- dimm_found = FALSE;
+ dimm_found = false;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
num_of_bytes = 0;
total_size = 0;
iic0_dimm_addr[dimm_num], total_size);
if ((num_of_bytes != 0) && (total_size != 0)) {
- dimm_populated[dimm_num] = TRUE;
- dimm_found = TRUE;
+ dimm_populated[dimm_num] = true;
+ dimm_found = true;
debug("DIMM slot %lu: populated\n", dimm_num);
} else {
- dimm_populated[dimm_num] = FALSE;
+ dimm_populated[dimm_num] = false;
debug("DIMM slot %lu: Not populated\n", dimm_num);
}
}
- if (dimm_found == FALSE) {
+ if (dimm_found == false) {
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
spd_ddr_init_hang ();
}
unsigned long dimm_type;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
+ if (dimm_populated[dimm_num] == true) {
dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
switch (dimm_type) {
case 1:
unsigned long val;
#ifdef CONFIG_DDR_ECC
- ecc_enabled = TRUE;
+ ecc_enabled = true;
#else
- ecc_enabled = FALSE;
+ ecc_enabled = false;
#endif
- dimm_32bit = FALSE;
- dimm_64bit = FALSE;
- buf0 = FALSE;
- buf1 = FALSE;
+ dimm_32bit = false;
+ dimm_64bit = false;
+ buf0 = false;
+ buf1 = false;
/*------------------------------------------------------------------
* Set memory controller options reg 1, SDRAM_MCOPT1.
/* test ecc support */
ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
if (ecc != 0x02) /* ecc not supported */
- ecc_enabled = FALSE;
+ ecc_enabled = false;
/* test bank count */
bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
if (registered == 1) { /* DDR2 always buffered */
/* TODO: what about above comments ? */
mcopt1 |= SDRAM_MCOPT1_RDEN;
- buf0 = TRUE;
+ buf0 = true;
} else {
/* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
if ((attribute & 0x02) == 0x00) {
/* buffered not supported */
- buf0 = FALSE;
+ buf0 = false;
} else {
mcopt1 |= SDRAM_MCOPT1_RDEN;
- buf0 = TRUE;
+ buf0 = true;
}
}
}
if (registered == 1) {
/* DDR2 always buffered */
mcopt1 |= SDRAM_MCOPT1_RDEN;
- buf1 = TRUE;
+ buf1 = true;
} else {
if ((attribute & 0x02) == 0x00) {
/* buffered not supported */
- buf1 = FALSE;
+ buf1 = false;
} else {
mcopt1 |= SDRAM_MCOPT1_RDEN;
- buf1 = TRUE;
+ buf1 = true;
}
}
}
switch (data_width) {
case 72:
case 64:
- dimm_64bit = TRUE;
+ dimm_64bit = true;
break;
case 40:
case 32:
- dimm_32bit = TRUE;
+ dimm_32bit = true;
break;
default:
printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
}
}
- if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
+ if ((dimm_64bit == true) && (dimm_32bit == true)) {
printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
spd_ddr_init_hang ();
- }
- else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
+ } else if ((dimm_64bit == true) && (dimm_32bit == false)) {
mcopt1 |= SDRAM_MCOPT1_DMWD_64;
- } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
+ } else if ((dimm_64bit == false) && (dimm_32bit == true)) {
mcopt1 |= SDRAM_MCOPT1_DMWD_32;
} else {
printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
spd_ddr_init_hang ();
}
- if (ecc_enabled == TRUE)
+ if (ecc_enabled == true)
mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
else
mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
total_rank += dimm_rank;
total_dimm++;
if ((dimm_num == 0) && (total_dimm == 1))
- firstSlot = TRUE;
+ firstSlot = true;
else
- firstSlot = FALSE;
+ firstSlot = false;
}
}
if (dimm_type == SDRAM_DDR2) {
codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
- if ((total_dimm == 1) && (firstSlot == TRUE)) {
+ if ((total_dimm == 1) && (firstSlot == true)) {
if (total_rank == 1) { /* PUUU */
codt |= CALC_ODT_R(0);
modt0 = CALC_ODT_W(0);
modt2 = 0x00000000;
modt3 = 0x00000000;
}
- } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
+ } else if ((total_dimm == 1) && (firstSlot != true)) {
if (total_rank == 1) { /* UUPU */
codt |= CALC_ODT_R(2);
modt0 = 0x00000000;
* the dimm modules installed.
*-----------------------------------------------------------------*/
t_wr_ns = 0;
- cas_2_0_available = TRUE;
- cas_2_5_available = TRUE;
- cas_3_0_available = TRUE;
- cas_4_0_available = TRUE;
- cas_5_0_available = TRUE;
+ cas_2_0_available = true;
+ cas_2_5_available = true;
+ cas_3_0_available = true;
+ cas_4_0_available = true;
+ cas_5_0_available = true;
max_2_0_tcyc_ns_x_100 = 10;
max_2_5_tcyc_ns_x_100 = 10;
max_3_0_tcyc_ns_x_100 = 10;
max_4_0_tcyc_ns_x_100 = 10;
max_5_0_tcyc_ns_x_100 = 10;
- sdram_ddr1 = TRUE;
+ sdram_ddr1 = true;
/* loop through all the DIMM slots on the board */
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
/* If a dimm is installed in a particular slot ... */
if (dimm_populated[dimm_num] != SDRAM_NONE) {
if (dimm_populated[dimm_num] == SDRAM_DDR1)
- sdram_ddr1 = TRUE;
+ sdram_ddr1 = true;
else
- sdram_ddr1 = FALSE;
+ sdram_ddr1 = false;
cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
} else {
if (cas_index != 0)
cas_index++;
- cas_4_0_available = FALSE;
+ cas_4_0_available = false;
}
if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
} else {
if (cas_index != 0)
cas_index++;
- cas_3_0_available = FALSE;
+ cas_3_0_available = false;
}
if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
} else {
if (cas_index != 0)
cas_index++;
- cas_2_5_available = FALSE;
+ cas_2_5_available = false;
}
if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
} else {
if (cas_index != 0)
cas_index++;
- cas_2_0_available = FALSE;
+ cas_2_0_available = false;
}
} else {
/*
} else {
if (cas_index != 0)
cas_index++;
- cas_5_0_available = FALSE;
+ cas_5_0_available = false;
}
if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
} else {
if (cas_index != 0)
cas_index++;
- cas_4_0_available = FALSE;
+ cas_4_0_available = false;
}
if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
} else {
if (cas_index != 0)
cas_index++;
- cas_3_0_available = FALSE;
+ cas_3_0_available = false;
}
}
}
debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
- if (sdram_ddr1 == TRUE) { /* DDR1 */
- if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
+ if (sdram_ddr1 == true) { /* DDR1 */
+ if ((cas_2_0_available == true) &&
+ (sdram_freq <= cycle_2_0_clk)) {
mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
*selected_cas = DDR_CAS_2;
- } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
+ } else if ((cas_2_5_available == true) &&
+ (sdram_freq <= cycle_2_5_clk)) {
mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
*selected_cas = DDR_CAS_2_5;
- } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
+ } else if ((cas_3_0_available == true) &&
+ (sdram_freq <= cycle_3_0_clk)) {
mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
*selected_cas = DDR_CAS_3;
} else {
debug("cas_3_0_available=%d\n", cas_3_0_available);
debug("cas_4_0_available=%d\n", cas_4_0_available);
debug("cas_5_0_available=%d\n", cas_5_0_available);
- if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
+ if ((cas_3_0_available == true) &&
+ (sdram_freq <= cycle_3_0_clk)) {
mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
*selected_cas = DDR_CAS_3;
- } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
+ } else if ((cas_4_0_available == true) &&
+ (sdram_freq <= cycle_4_0_clk)) {
mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
*selected_cas = DDR_CAS_4;
- } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
+ } else if ((cas_5_0_available == true) &&
+ (sdram_freq <= cycle_5_0_clk)) {
mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
*selected_cas = DDR_CAS_5;
} else {
}
}
- if (sdram_ddr1 == TRUE)
+ if (sdram_ddr1 == true)
mmode |= SDRAM_MMODE_WR_DDR1;
else {
t_wpc_ns = 0;
t_wtr_ns = 0;
t_rpc_ns = 0;
- sdram_ddr1 = TRUE;
+ sdram_ddr1 = true;
/* loop through all the DIMM slots on the board */
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
/* If a dimm is installed in a particular slot ... */
if (dimm_populated[dimm_num] != SDRAM_NONE) {
if (dimm_populated[dimm_num] == SDRAM_DDR2)
- sdram_ddr1 = TRUE;
+ sdram_ddr1 = true;
else
- sdram_ddr1 = FALSE;
+ sdram_ddr1 = false;
t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
break;
}
- if (sdram_ddr1 == TRUE) { /* DDR1 */
+ if (sdram_ddr1 == true) { /* DDR1 */
if (sdram_freq < 200000000) {
sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
current_pass_length = 0;
current_fail_length = 0;
current_start = 0;
- fail_found = FALSE;
- pass_found = FALSE;
+ fail_found = false;
+ pass_found = false;
/*
* get the delay line calibration register value
* See if the rffd value passed.
*-----------------------------------------------------------------*/
if (short_mem_test()) {
- if (fail_found == TRUE) {
- pass_found = TRUE;
+ if (fail_found == true) {
+ pass_found = true;
if (current_pass_length == 0)
current_start = rffd;
current_fail_length++;
if (current_fail_length >= (dly_val >> 2)) {
- if (fail_found == FALSE) {
- fail_found = TRUE;
- } else if (pass_found == TRUE) {
+ if (fail_found == false)
+ fail_found = true;
+ else if (pass_found == true)
break;
- }
}
}
} /* for rffd */
current_pass_length = 0;
current_fail_length = 0;
current_start = 0;
- window_found = FALSE;
- fail_found = FALSE;
- pass_found = FALSE;
+ window_found = false;
+ fail_found = false;
+ pass_found = false;
for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
mfsdram(SDRAM_RQDC, rqdc_reg);
* See if the rffd value passed.
*-----------------------------------------------------------------*/
if (short_mem_test()) {
- if (fail_found == TRUE) {
- pass_found = TRUE;
+ if (fail_found == true) {
+ pass_found = true;
if (current_pass_length == 0)
current_start = rqfd;
current_pass_length = 0;
current_fail_length++;
- if (fail_found == FALSE) {
- fail_found = TRUE;
- } else if (pass_found == TRUE) {
- window_found = TRUE;
+ if (fail_found == false) {
+ fail_found = true;
+ } else if (pass_found == true) {
+ window_found = true;
break;
}
}
/*------------------------------------------------------------------
* Make sure we found the valid read passing window. Halt if not
*-----------------------------------------------------------------*/
- if (window_found == FALSE) {
+ if (window_found == false) {
if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
putc('\b');
putc(slash[loopi++ % 8]);
mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
SDRAM_MCOPT1_MCHK_NON);
- window_found = FALSE;
- begin_found[0] = FALSE;
- end_found[0] = FALSE;
- search_end[0] = FALSE;
- begin_found[1] = FALSE;
- end_found[1] = FALSE;
- search_end[1] = FALSE;
+ window_found = false;
+ begin_found[0] = false;
+ end_found[0] = false;
+ search_end[0] = false;
+ begin_found[1] = false;
+ end_found[1] = false;
+ search_end[1] = false;
for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
* See if the rffd value passed.
*-----------------------------------------------------------------*/
if (i < NUMMEMTESTS) {
- if ((end_found[dimm_num] == FALSE) &&
- (search_end[dimm_num] == TRUE)) {
- end_found[dimm_num] = TRUE;
+ if ((end_found[dimm_num] == false) &&
+ (search_end[dimm_num] == true)) {
+ end_found[dimm_num] = true;
}
- if ((end_found[0] == TRUE) &&
- (end_found[1] == TRUE))
+ if ((end_found[0] == true) &&
+ (end_found[1] == true))
break;
} else {
- if (begin_found[dimm_num] == FALSE) {
- begin_found[dimm_num] = TRUE;
- search_end[dimm_num] = TRUE;
+ if (begin_found[dimm_num] == false) {
+ begin_found[dimm_num] = true;
+ search_end[dimm_num] = true;
}
}
} else {
- begin_found[dimm_num] = TRUE;
- end_found[dimm_num] = TRUE;
+ begin_found[dimm_num] = true;
+ end_found[dimm_num] = true;
}
}
- if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
- window_found = TRUE;
+ if ((begin_found[0] == true) && (begin_found[1] == true))
+ window_found = true;
/*------------------------------------------------------------------
* Make sure we found the valid read passing window. Halt if not
*-----------------------------------------------------------------*/
- if (window_found == FALSE) {
+ if (window_found == false) {
printf("ERROR: Cannot determine a common read delay for the "
"DIMM(s) installed.\n");
spd_ddr_init_hang ();
/*-----------------------------------------------------------------------------+
* Defines
*-----------------------------------------------------------------------------*/
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
#define MAXDIMMS 2
#define MAXRANKS 2
unsigned long num_dimm_banks)
{
unsigned long dimm_num;
- unsigned long dimm_found = FALSE;
+ unsigned long dimm_found = false;
unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1;
unsigned char num_of_bytes;
unsigned char total_size;
"\n\n");
spd_ddr_init_hang();
}
- dimm_found = TRUE;
+ dimm_found = true;
debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM"
"\n", dimm_num, ranks_on_dimm);
if (ranks_on_dimm > max_ranks_per_dimm) {
debug("DIMM slot %lu: Not populated\n", dimm_num);
}
}
- if (dimm_found == FALSE) {
+ if (dimm_found == false) {
printf("ERROR: No memory installed.\n");
printf("Install at least one DDR2 DIMM.\n\n");
spd_ddr_init_hang();
/* Check for ECC */
if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) &
0x02)) {
- ecc_available = FALSE;
+ ecc_available = false;
}
}
}
* OUTPUT:
* None.
* RETURN:
-* False for invalid size, true otherwise.
+* false for invalid size, true otherwise.
*
* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
*
* None.
*
* RETURN:
-* False for invalid size, true otherwise.
+* false for invalid size, true otherwise.
*
* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
*
* None.
*
* RETURN:
-* False for invalid size, true otherwise.
+* false for invalid size, true otherwise.
*
*******************************************************************************/
bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
* None.
*
* RETURN:
-* False for invalid size, true otherwise.
+* false for invalid size, true otherwise.
*
*******************************************************************************/
bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window,
* OUTPUT:
* None.
* RETURN:
-* True for a closed window, false otherwise .
+* true for a closed window, false otherwise .
*******************************************************************************/
MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window)
{
* None.
*
* RETURN:
-* True for success, false otherwise.
+* true for success, false otherwise.
*
*******************************************************************************/
**************************************************************************
**************************************************************************
*************************************************************************/
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
#ifndef MAX_SKB_FRAGS
#define MAX_SKB_FRAGS 0
* None.
*
* RETURN:
-* True for success, false otherwise.
+* true for success, false otherwise.
*
*******************************************************************************/
**************************************************************************
**************************************************************************
*************************************************************************/
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
#ifndef MAX_SKB_FRAGS
#define MAX_SKB_FRAGS 0
#define _1G 0x40000000
#define _2G 0x80000000
-#ifndef BOOL_WAS_DEFINED
-#define BOOL_WAS_DEFINED
-typedef enum _bool{false,true} bool;
-#endif
-
/* Little to Big endian conversion macros */
#ifdef LE /* Little Endian */
pvr = get_pvr();
if (pvr == PVR_POWERPC_440EP_PASS1)
- return TRUE;
+ return true;
else if (pvr == PVR_POWERPC_440EP_PASS2)
- return FALSE;
+ return false;
else {
printf("brdutil error 3\n");
for (;;)
;
}
- return(FALSE);
+ return false;
}
/*----------------------------------------------------------------------------+
int is_nand_selected(void)
{
#ifdef CONFIG_BAMBOO_NAND
- return TRUE;
+ return true;
#else
- return FALSE;
+ return false;
#endif
}
unsigned char config_on_ebc_cs4_is_small_flash(void)
{
/* Not implemented yet => returns constant value */
- return TRUE;
+ return true;
}
/*----------------------------------------------------------------------------+
/*-------------------------------------------------------------------------+
| PPC440EP Pass1
+-------------------------------------------------------------------------*/
- if (is_powerpc440ep_pass1() == TRUE) {
+ if (is_powerpc440ep_pass1() == true) {
switch(bootstrap_settings) {
case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
/* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
/*------------------------------------------------------------------------- */
ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
- if ((is_nand_selected()) == TRUE) {
+ if ((is_nand_selected()) == true) {
/* NAND Flash */
ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
/*------------------------------------------------------------------------- */
ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
- if ((is_nand_selected()) == TRUE) {
+ if ((is_nand_selected()) == true) {
/* NAND Flash */
ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
ebc0_cs0_bnap_value = 0;
ebc0_cs0_bncr_value = 0;
- if ((is_nand_selected()) == TRUE) {
+ if ((is_nand_selected()) == true) {
/* NAND Flash */
ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
ebc0_cs3_bncr_value = 0;
}
- if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
+ if ((config_on_ebc_cs4_is_small_flash()) == true) {
/* Small Flash */
ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
#define PVR_POWERPC_440EP_PASS1 0x42221850
#define PVR_POWERPC_440EP_PASS2 0x422218D3
-#define TRUE 1
-#define FALSE 0
-
#define GPIO0 0
#define GPIO1 1
#define DEBUGF(fmt,args...)
#endif
-#define FALSE 0
-#define TRUE 1
-
int board_early_init_f (void)
{
/*----------------------------------------------------------------------------+
#define V_ULONG(a) (*(volatile unsigned long *)( a ))
#define V_BYTE(a) (*(volatile unsigned char *)( a ))
-#define TRUE 0x1
-#define FALSE 0x0
#define BUFFER_SIZE 0x80000
#define NO_COMMAND 0
#define GET_CODES 1
nValue = *(volatile unsigned short *)addr;
SSYNC();
*pnValue = nValue;
- return TRUE;
+ return true;
}
int poll_toggle_bit(long lOffset)
long ulSectorOff = 0x0;
if ((nBlock < 0) || (nBlock > AFP_NumSectors))
- return FALSE;
+ return false;
ulSectorOff = (address - CONFIG_SYS_FLASH_BASE);
#define YELLOW (0xD292D210) /* yellow pixel pattern */
#define WHITE (0xFE80FE80) /* white pixel pattern */
-#define true 1
-#define false 0
-
typedef struct {
unsigned int sav;
unsigned int eav;
/*
* Big epson detected
*/
- reg_byte_swap = FALSE;
+ reg_byte_swap = false;
palette_index = 0x1e2;
palette_value = 0x1e4;
lcd_depth = 16;
/*
* Big epson detected (with register swap bug)
*/
- reg_byte_swap = TRUE;
+ reg_byte_swap = true;
palette_index = 0x1e3;
palette_value = 0x1e5;
lcd_depth = 16;
/*
* Small epson detected (704)
*/
- reg_byte_swap = FALSE;
+ reg_byte_swap = false;
palette_index = 0x15;
palette_value = 0x17;
lcd_depth = 8;
/*
* Small epson detected (705)
*/
- reg_byte_swap = FALSE;
+ reg_byte_swap = false;
palette_index = 0x15;
palette_value = 0x17;
lcd_depth = 8;
/*
* S1D13505 detected
*/
- reg_byte_swap = TRUE;
+ reg_byte_swap = true;
palette_index = 0x25;
palette_value = 0x27;
lcd_depth = 16;
#define LOAD_LONG(data) SWAP_LONG(data)
#define LOAD_SHORT(data) SWAP_SHORT(data)
-#ifndef FALSE
-#define FALSE 0
-#define TRUE (!FALSE)
-#endif
-
#define S1D_WRITE_PALETTE(p,i,r,g,b) \
{ \
out_8(&((uchar*)(p))[palette_index], (uchar)(i)); \
* None.
*
* RETURN:
-* True for success, false otherwise.
+* true for success, false otherwise.
*
*******************************************************************************/
**************************************************************************
**************************************************************************
*************************************************************************/
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
#ifndef MAX_SKB_FRAGS
#define MAX_SKB_FRAGS 0
#define OK 0
#define ERROR (-1)
-#define TRUE 1
-#define FALSE 0
-
-
extern u_long pci9054_iobase;
}
}
- return TRUE;
+ return true;
}
{
debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
__LINE__);
- fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
+ fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
}
int fpga_pre_config_fn(int cookie)
{
debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
- fpga_reset(TRUE);
+ fpga_reset(true);
/* release init# */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
/* enable PLD0..7 pins */
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
- fpga_reset(TRUE);
+ fpga_reset(true);
udelay (100);
- fpga_reset(FALSE);
+ fpga_reset(false);
udelay (100);
FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
__FUNCTION__, __LINE__);
/* make sure program pin is inactive */
- ngcc_fpga_pgm_fn (FALSE, FALSE, 0);
+ ngcc_fpga_pgm_fn(false, false, 0);
}
/*
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
- ngcc_fpga_reset(TRUE);
+ ngcc_fpga_reset(true);
FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
- ngcc_fpga_reset(TRUE);
+ ngcc_fpga_reset(true);
return 0;
}
debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
udelay (100);
- ngcc_fpga_reset(FALSE);
+ ngcc_fpga_reset(false);
FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
#include "eth.h"
#include "eth_addrtbl.h"
-#define TRUE 1
-#define FALSE 0
-
#define PRINTF printf
#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
* rd - the RD field in the address table.
* Outputs
* address table entry is added.
- * TRUE if success.
- * FALSE if table full
+ * true if success.
+ * false if table full
*/
int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip)
{
if (i == HOP_NUMBER) {
PRINTF ("addGT64260addressTableEntry: table section is full\n");
- return (FALSE);
+ return false;
}
/*
entry->hi = newHi;
entry->lo = newLo;
DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE);
- return (TRUE);
+ return true;
}
#endif /* CONFIG_GT_USE_MAC_HASH_TABLE */
{
PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__,
__LINE__);
- fpga_pgm_fn (FALSE, FALSE, 0); /* make sure program pin is inactive */
+ fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
}
int fpga_pre_config_fn (int cookie)
{
PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
- fpga_reset (TRUE);
+ fpga_reset(true);
return 0;
}
int rc;
PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
- fpga_reset (TRUE);
+ fpga_reset(true);
udelay (1000);
- fpga_reset (FALSE);
+ fpga_reset(false);
udelay (1000);
/*
int overwrite_console(void)
{
- /* return TRUE if console should be overwritten */
+ /* return true if console should be overwritten */
return 0;
}
}
/*
- * flashWritable returns TRUE if a range contains all F's.
+ * flashWritable returns true if a range contains all F's.
*/
STATUS flashWritable (flash_dev_t * dev, int pos, int len)
#define PRINTF(fmt,args...)
#endif
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
#if defined(CONFIG_PIP405)
extern int drv_isa_kbd_init (void);
out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */
out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */
if(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
}
void close_cfg_super_IO(int address)
void isa_sio_setup(void)
{
- if(open_cfg_super_IO(SIO_CFG_PORT)==TRUE)
+ if (open_cfg_super_IO(SIO_CFG_PORT) == true)
{
isa_sio_loadtable();
close_cfg_super_IO(0x3F0);
#undef SDRAM_DEBUG
#define ENABLE_ECC /* for ecc boards */
-#define FALSE 0
-#define TRUE 1
/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
#ifndef __ldiv_t_defined
int overwrite_console (void)
{
- return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */
+ /* return true if console should be overwritten */
+ return ((in8(PLD_EXT_CONF_REG) & 0x1) == 0);
}
#undef SDRAM_DEBUG
-#define FALSE 0
-#define TRUE 1
-
/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
#ifndef __ldiv_t_defined
typedef struct {
int overwrite_console (void)
{
- return (in8 (CONFIG_PORT_ADDR) & 0x1); /* return TRUE if console should be overwritten */
+ /* return true if console should be overwritten */
+ return in8(CONFIG_PORT_ADDR) & 0x1;
}
void user_led0 (unsigned char on)
{
- if (on == TRUE)
+ if (on == true)
out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
else
out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
void user_led1 (unsigned char on)
{
- if (on == TRUE)
+ if (on == true)
out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
else
out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
* None.
*
* RETURN:
-* True for success, false otherwise.
+* true for success, false otherwise.
*
*******************************************************************************/
**************************************************************************
**************************************************************************
*************************************************************************/
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
#ifndef MAX_SKB_FRAGS
#define MAX_SKB_FRAGS 0
if (*brg_ptr & CPM_BRG_DIV16) {
/* DIV16 active */
- return (TRUE);
+ return true;
}
else {
/* DIV16 inactive */
- return (FALSE);
+ return false;
}
}
* MA 02111-1307 USA
*/
-#ifndef FALSE
-#define FALSE 0
-#define TRUE (!FALSE)
-#endif
-
#define SLRCLK_EN_MASK 0x00040000 /* PA13 - SLRCLK_EN* */
#define MIN_SAMPLE_RATE 4000 /* Minimum sample rate */
static int fpga_pre_config_fn(int cookie)
{
debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
- fpga_reset(TRUE);
+ fpga_reset(true);
return 0;
}
debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
- fpga_reset(TRUE);
+ fpga_reset(true);
udelay(100);
- fpga_reset(FALSE);
+ fpga_reset(false);
udelay(100);
return rc;
static void fpga_serialslave_init(void)
{
debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
- fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
+ fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
}
static int expi_setup(int freq)
{
debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
- fpga_reset(TRUE);
+ fpga_reset(true);
udelay(100);
- fpga_reset(FALSE);
+ fpga_reset(false);
return 0;
}
* F_INSTR - output raw instruction.
* F_LINENO - show line # info if available.
*
- * Returns TRUE if the area was successfully disassembled or FALSE if
+ * Returns true if the area was successfully disassembled or false if
* a problem was encountered with accessing the memory.
*/
for (i = 0; i < num_instr; ++i, memaddr += 4, ctx.virtual += 4) {
#ifdef USE_SOURCE_CODE
if (ctx.flags & F_LINENO) {
- if ((line_info_from_addr ((Elf32_Word) ctx.virtual, filename,
- funcname, &line_no) == TRUE) &&
+ if ((line_info_from_addr ((Elf32_Word) ctx.virtual,
+ filename, funcname, &line_no) == true) &&
((line_no != last_line_no) ||
(strcmp (last_funcname, funcname) != 0))) {
print_source_line (filename, funcname, line_no, pfunc);
#ifdef USE_SOURCE_CODE
if (ctx.flags & F_SYMBOL) {
if ((symname =
- symbol_name_from_addr ((Elf32_Word) ctx.virtual,
- TRUE, 0)) != 0) {
+ symbol_name_from_addr((Elf32_Word) ctx.virtual,
+ true, 0)) != 0) {
cursym = symname;
symoffset = 0;
} else {
if ((cursym == 0) &&
((symname =
- symbol_name_from_addr ((Elf32_Word) ctx.virtual,
- FALSE, &symoffset)) != 0)) {
+ symbol_name_from_addr((Elf32_Word) ctx.virtual,
+ false, &symoffset)) != 0)) {
cursym = symname;
} else {
symoffset += 4;
}
if (((ctx.flags & F_SIMPLE) == 0) ||
- (ctx.op->hfunc == 0) || ((*ctx.op->hfunc) (&ctx) == FALSE)) {
+ (ctx.op->hfunc == 0) ||
+ ((*ctx.op->hfunc) (&ctx) == false)) {
sprintf (&ctx.data[ctx.datalen], "%-7s ", ctx.op->name);
ctx.datalen += 8;
print_operands (&ctx);
(*pfunc) (ctx.data);
}
- return TRUE;
+ return true;
} /* disppc */
\f
* value The address of an unsigned long to be filled in
* with the value of the operand if it is found. This
* will only be filled in if the function returns
- * TRUE. This may be passed as 0 if the value is
+ * true. This may be passed as 0 if the value is
* not required.
*
- * Returns TRUE if the operand was found or FALSE if it was not.
+ * Returns true if the operand was found or false if it was not.
*/
int get_operand_value (struct opcode *op, unsigned long instr,
/*------------------------------------------------------------*/
if (field > n_operands) {
- return FALSE; /* bad operand ?! */
+ return false; /* bad operand ?! */
}
/* Walk through the operands and list each in order */
if (value) {
*value = (instr >> opr->shift) & ((1 << opr->bits) - 1);
}
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
} /* operand_value */
\f
* Arguments:
* ctx A pointer to the disassembler context record.
*
- * Returns TRUE if the simpler form was printed or FALSE if it was not.
+ * Returns true if the simpler form was printed or false if it was not.
*/
int handle_bc (struct ppc_ctx *ctx)
/*------------------------------------------------------------*/
- if (get_operand_value (ctx->op, ctx->instr, O_BO, &bo) == FALSE)
- return FALSE;
+ if (get_operand_value(ctx->op, ctx->instr, O_BO, &bo) == false)
+ return false;
- if (get_operand_value (ctx->op, ctx->instr, O_BI, &bi) == FALSE)
- return FALSE;
+ if (get_operand_value(ctx->op, ctx->instr, O_BI, &bi) == false)
+ return false;
if ((bo == 12) && (bi == 0)) {
ctx->op = &blt;
sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name);
ctx->datalen += 8;
print_operands (ctx);
- return TRUE;
+ return true;
} else if ((bo == 4) && (bi == 10)) {
ctx->op = =⃥
sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name);
ctx->datalen += 8;
print_operands (ctx);
- return TRUE;
+ return true;
} else if ((bo == 16) && (bi == 0)) {
ctx->op = &bdnz;
sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name);
ctx->datalen += 8;
print_operands (ctx);
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
} /* handle_blt */
\f
* pfunc The address of a function to call to print the output.
*
*
- * Returns TRUE if it was able to output the line info, or false if it was
+ * Returns true if it was able to output the line info, or false if it was
* not.
*/
sprintf (out_buf, "%s %s(): line %d", filename, funcname, line_no);
(*pfunc) (out_buf);
- return TRUE;
+ return true;
} /* print_source_line */
\f
* Arguments:
* nextaddr The address (to be filled in) of the next
* instruction to execute. This will only be a valid
- * address if TRUE is returned.
+ * address if true is returned.
*
* step_over A flag indicating how to compute addresses for
* branch statements:
- * TRUE = Step over the branch (next)
- * FALSE = step into the branch (step)
+ * true = Step over the branch (next)
+ * false = step into the branch (step)
*
- * Returns TRUE if it was able to compute the address. Returns FALSE if
+ * Returns true if it was able to compute the address. Returns false if
* it has a problem reading the current instruction or one of the registers.
*/
if (nextaddr == 0 || regs == 0) {
printf ("find_next_address: bad args");
- return FALSE;
+ return false;
}
pc = regs->nip & 0xfffffffc;
if ((op = find_opcode (instr)) == (struct opcode *) 0) {
printf ("find_next_address: can't parse opcode 0x%lx", instr);
- return FALSE;
+ return false;
}
ctr = regs->ctr;
!get_operand_value (op, instr, O_BI, &bi) ||
!get_operand_value (op, instr, O_AA, &aa) ||
!get_operand_value (op, instr, O_LK, &lk))
- return FALSE;
+ return false;
if ((addr & (1 << 13)) != 0)
addr = addr - (1 << 14);
if (!get_operand_value (op, instr, O_LI, &addr) ||
!get_operand_value (op, instr, O_AA, &aa) ||
!get_operand_value (op, instr, O_LK, &lk))
- return FALSE;
+ return false;
if ((addr & (1 << 23)) != 0)
addr = addr - (1 << 24);
if (!get_operand_value (op, instr, O_BO, &bo) ||
!get_operand_value (op, instr, O_BI, &bi) ||
!get_operand_value (op, instr, O_LK, &lk))
- return FALSE;
+ return false;
addr = ctr;
aa = 1;
if (!get_operand_value (op, instr, O_BO, &bo) ||
!get_operand_value (op, instr, O_BI, &bi) ||
!get_operand_value (op, instr, O_LK, &lk))
- return FALSE;
+ return false;
addr = lr;
aa = 1;
step = next = pc + 4;
}
- if (step_over == TRUE)
+ if (step_over == true)
*(unsigned long *) nextaddr = next;
else
*(unsigned long *) nextaddr = step;
- return TRUE;
+ return true;
} /* find_next_address */
return 1;
}
- if (!find_next_address ((unsigned char *) &addr, FALSE, bug_ctx.regs))
+ if (!find_next_address((unsigned char *) &addr, false, bug_ctx.regs))
return 1;
if (bug_ctx.set)
return 1;
}
- if (!find_next_address ((unsigned char *) &addr, TRUE, bug_ctx.regs))
+ if (!find_next_address((unsigned char *) &addr, true, bug_ctx.regs))
return 1;
if (bug_ctx.set)
#define PRINTF(fmt,args...)
#endif
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
/*#if defined(CONFIG_CMD_DATE) */
/*#include <rtc.h> */
/*#endif */
timeout--;
udelay(10);
if(timeout==0) /* timeout occured */
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
/* reads a byte from the FIFO of the FDC and checks direction and RQM bit
c=(unsigned char)read_fdc_byte();
printf("Error: more output: %x\n",c);
}
- return TRUE;
+ return true;
}
udelay(10);
fdc_need_more_output();
if(timeout==0) /* timeout occured */
- return FALSE;
+ return false;
}
write_fdc_reg(FDC_FIFO,val);
- return TRUE;
+ return true;
}
/* sets up all FDC commands and issues it to the FDC. If
}
for(i=0;i<pCMD->cmdlen;i++) {
/* PRINTF("write cmd%d = 0x%02X\n",i,pCMD->cmd[i]); */
- if(write_fdc_byte(pCMD->cmd[i])==FALSE) {
+ if (write_fdc_byte(pCMD->cmd[i]) == false) {
PRINTF("Error: timeout while issue cmd%d\n",i);
- return FALSE;
+ return false;
}
}
timeout=FDC_TIME_OUT;
timeout--;
if(timeout==0) {
PRINTF(" timeout while reading result%d MSR=0x%02X\n",i,read_fdc_reg(FDC_MSR));
- return FALSE;
+ return false;
}
}
pCMD->result[i]=(unsigned char)read_fdc_byte();
}
- return TRUE;
+ return true;
}
/* selects the drive assigned in the cmd structur and
int fdc_recalibrate(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG)
{
pCMD->cmd[COMMAND]=FDC_CMD_RECALIBRATE;
- if(fdc_issue_cmd(pCMD,pFG)==FALSE)
- return FALSE;
- while(wait_for_fdc_int()!=TRUE);
+ if (fdc_issue_cmd(pCMD, pFG) == false)
+ return false;
+ while (wait_for_fdc_int() != true);
+
pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT;
return(fdc_issue_cmd(pCMD,pFG));
}
int fdc_seek(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG)
{
pCMD->cmd[COMMAND]=FDC_CMD_SEEK;
- if(fdc_issue_cmd(pCMD,pFG)==FALSE)
- return FALSE;
- while(wait_for_fdc_int()!=TRUE);
+ if (fdc_issue_cmd(pCMD, pFG) == false)
+ return false;
+ while (wait_for_fdc_int() != true);
+
pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT;
return(fdc_issue_cmd(pCMD,pFG));
}
for(i=0;i<7;i++) {
pCMD->result[i]=(unsigned char)read_fdc_byte();
}
- return TRUE;
+ return true;
}
/* reads data from FDC, seek commands are issued automatic */
retriesrw=0;
retriescal=0;
offset=0;
- if(fdc_seek(pCMD,pFG)==FALSE) {
+ if (fdc_seek(pCMD, pFG) == false) {
stop_fdc_drive(pCMD);
if (flags)
enable_interrupts();
- return FALSE;
+ return false;
}
if((pCMD->result[STATUS_0]&0x20)!=0x20) {
printf("Seek error Status: %02X\n",pCMD->result[STATUS_0]);
stop_fdc_drive(pCMD);
if (flags)
enable_interrupts();
- return FALSE;
+ return false;
}
/* now determine the next seek point */
/* lastblk=pCMD->blnr + blocks; */
retryrw:
len=sect_size * readblk;
pCMD->cmd[COMMAND]=FDC_CMD_READ;
- if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
+ if (fdc_issue_cmd(pCMD, pFG) == false) {
stop_fdc_drive(pCMD);
if (flags)
enable_interrupts();
- return FALSE;
+ return false;
}
for (i=0;i<len;i++) {
timeout=FDC_TIME_OUT;
stop_fdc_drive(pCMD);
if (flags)
enable_interrupts();
- return FALSE;
+ return false;
}
else {
PRINTF(" trying to recalibrate Try %d\n",retriescal);
- if(fdc_recalibrate(pCMD,pFG)==FALSE) {
+ if (fdc_recalibrate(pCMD, pFG) == false) {
stop_fdc_drive(pCMD);
if (flags)
enable_interrupts();
- return FALSE;
+ return false;
}
retriesrw=0;
goto retrycal;
} /* else >FDC_RW_RETRIES */
}/* if output */
timeout--;
- }while(TRUE);
+ } while (true);
} /* for len */
/* the last sector of a track or all data has been read,
* we need to get the results */
readblk=blocks;
retrycal:
/* a seek is necessary */
- if(fdc_seek(pCMD,pFG)==FALSE) {
+ if (fdc_seek(pCMD, pFG) == false) {
stop_fdc_drive(pCMD);
if (flags)
enable_interrupts();
- return FALSE;
+ return false;
}
if((pCMD->result[STATUS_0]&0x20)!=0x20) {
PRINTF("Seek error Status: %02X\n",pCMD->result[STATUS_0]);
stop_fdc_drive(pCMD);
- return FALSE;
+ return false;
}
- }while(TRUE); /* start over */
+ } while (true); /* start over */
stop_fdc_drive(pCMD); /* switch off drive */
if (flags)
enable_interrupts();
- return TRUE;
+ return true;
}
/* Scan all drives and check if drive is present and disk is inserted */
pCMD->drive=drives;
select_fdc_drive(pCMD);
pCMD->blnr=0; /* set to the 1st block */
- if(fdc_recalibrate(pCMD,pFG)==FALSE)
+ if (fdc_recalibrate(pCMD, pFG) == false)
continue;
if((pCMD->result[STATUS_0]&0x10)==0x10)
continue;
/* ok drive connected check for disk */
state|=(1<<drives);
pCMD->blnr=pFG->size; /* set to the last block */
- if(fdc_seek(pCMD,pFG)==FALSE)
+ if (fdc_seek(pCMD, pFG) == false)
continue;
pCMD->blnr=0; /* set to the 1st block */
- if(fdc_recalibrate(pCMD,pFG)==FALSE)
+ if (fdc_recalibrate(pCMD, pFG) == false)
continue;
pCMD->cmd[COMMAND]=FDC_CMD_READ_ID;
- if(fdc_issue_cmd(pCMD,pFG)==FALSE)
+ if (fdc_issue_cmd(pCMD, pFG) == false)
continue;
state|=(0x10<<drives);
}
((state&(0x10<<i))==(0x10<<i)) ? pFG->name : "");
}
pCMD->flags=state;
- return TRUE;
+ return true;
}
write_fdc_reg(FDC_CCR,pFG->rate);
/* then initialize the DSR */
write_fdc_reg(FDC_DSR,pFG->rate);
- if(wait_for_fdc_int()==FALSE) {
+ if (wait_for_fdc_int() == false) {
PRINTF("Time Out after writing CCR\n");
- return FALSE;
+ return false;
}
/* now issue sense Interrupt and status command
* assuming only one drive present (drive 0) */
for(i=0;i<4;i++) {
/* issue sense interrupt for all 4 possible drives */
pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT;
- if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
+ if (fdc_issue_cmd(pCMD, pFG) == false) {
PRINTF("Sense Interrupt for drive %d failed\n",i);
}
}
pCMD->drive=drive;
select_fdc_drive(pCMD);
pCMD->cmd[COMMAND]=FDC_CMD_CONFIGURE;
- if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
+ if (fdc_issue_cmd(pCMD, pFG) == false) {
PRINTF(" configure timeout\n");
stop_fdc_drive(pCMD);
- return FALSE;
+ return false;
}
/* issue specify command */
pCMD->cmd[COMMAND]=FDC_CMD_SPECIFY;
- if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
+ if (fdc_issue_cmd(pCMD, pFG) == false) {
PRINTF(" specify timeout\n");
stop_fdc_drive(pCMD);
- return FALSE;
+ return false;
}
/* then, we clear the reset in the DOR */
/* fdc_check_drive(pCMD,pFG); */
/* write_fdc_reg(FDC_DOR,0x04); */
- return TRUE;
+ return true;
}
#if defined(CONFIG_CMD_FDOS)
FDC_COMMAND_STRUCT *pCMD = &cmd;
/* setup FDC and scan for drives */
- if(fdc_setup(drive,pCMD,pFG)==FALSE) {
+ if (fdc_setup(drive, pCMD, pFG) == false) {
printf("\n** Error in setup FDC **\n");
- return FALSE;
+ return false;
}
- if(fdc_check_drive(pCMD,pFG)==FALSE) {
+ if (fdc_check_drive(pCMD, pFG) == false) {
printf("\n** Error in check_drives **\n");
- return FALSE;
+ return false;
}
if((pCMD->flags&(1<<drive))==0) {
/* drive not available */
printf("\n** Drive %d not available **\n",drive);
- return FALSE;
+ return false;
}
if((pCMD->flags&(0x10<<drive))==0) {
/* no disk inserted */
printf("\n** No disk inserted in drive %d **\n",drive);
- return FALSE;
+ return false;
}
/* ok, we have a valid source */
pCMD->drive=drive;
/* read first block */
pCMD->blnr=0;
- return TRUE;
+ return true;
}
/**************************************************************************
* int fdc_fdos_seek
return CMD_RET_USAGE;
}
/* setup FDC and scan for drives */
- if(fdc_setup(boot_drive,pCMD,pFG)==FALSE) {
+ if (fdc_setup(boot_drive, pCMD, pFG) == false) {
printf("\n** Error in setup FDC **\n");
return 1;
}
- if(fdc_check_drive(pCMD,pFG)==FALSE) {
+ if (fdc_check_drive(pCMD, pFG) == false) {
printf("\n** Error in check_drives **\n");
return 1;
}
pCMD->drive=boot_drive;
/* read first block */
pCMD->blnr=0;
- if(fdc_read_data((unsigned char *)addr,1,pCMD,pFG)==FALSE) {
+ if (fdc_read_data((unsigned char *)addr, 1, pCMD, pFG) == false) {
printf("\nRead error:");
for(i=0;i<7;i++)
printf("result%d: 0x%02X\n",i,pCMD->result[i]);
nrofblk++;
printf("Loading %ld Bytes (%d blocks) at 0x%08lx..\n",imsize,nrofblk,addr);
pCMD->blnr=0;
- if(fdc_read_data((unsigned char *)addr,nrofblk,pCMD,pFG)==FALSE) {
+ if (fdc_read_data((unsigned char *)addr, nrofblk, pCMD, pFG) == false) {
/* read image block */
printf("\nRead error:");
for(i=0;i<7;i++)
scsi_dev_desc[i].vendor[0]=0;
scsi_dev_desc[i].product[0]=0;
scsi_dev_desc[i].revision[0]=0;
- scsi_dev_desc[i].removable=FALSE;
+ scsi_dev_desc[i].removable = false;
scsi_dev_desc[i].if_type=IF_TYPE_SCSI;
scsi_dev_desc[i].dev=i;
scsi_dev_desc[i].part_type=PART_TYPE_UNKNOWN;
pccb->pdata=(unsigned char *)&tempbuff;
pccb->datalen=512;
scsi_setup_inquiry(pccb);
- if(scsi_exec(pccb)!=TRUE) {
+ if (scsi_exec(pccb) != true) {
if(pccb->contr_stat==SCSI_SEL_TIME_OUT) {
debug ("Selection timeout ID %d\n",pccb->target);
continue; /* selection timeout => assuming no device present */
continue; /* skip unknown devices */
}
if((modi&0x80)==0x80) /* drive is removable */
- scsi_dev_desc[scsi_max_devs].removable=TRUE;
+ scsi_dev_desc[scsi_max_devs].removable=true;
/* get info for this device */
scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].vendor[0],
&tempbuff[8], 8);
pccb->datalen=0;
scsi_setup_test_unit_ready(pccb);
- if(scsi_exec(pccb)!=TRUE) {
- if(scsi_dev_desc[scsi_max_devs].removable==TRUE) {
+ if (scsi_exec(pccb) != true) {
+ if (scsi_dev_desc[scsi_max_devs].removable == true) {
scsi_dev_desc[scsi_max_devs].type=perq;
goto removable;
}
debug("scsi_read_ext: startblk " LBAF
", blccnt %x buffer %lx\n",
start, smallblks, buf_addr);
- if(scsi_exec(pccb)!=TRUE) {
+ if (scsi_exec(pccb) != true) {
scsi_print_error(pccb);
blkcnt-=blks;
break;
}
debug("%s: startblk " LBAF ", blccnt %x buffer %lx\n",
__func__, start, smallblks, buf_addr);
- if (scsi_exec(pccb) != TRUE) {
+ if (scsi_exec(pccb) != true) {
scsi_print_error(pccb);
blkcnt -= blks;
break;
pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
pccb->datalen = 8;
- if (scsi_exec(pccb) != TRUE)
+ if (scsi_exec(pccb) != true)
return 1;
*capacity = ((lbaint_t)pccb->pdata[0] << 24) |
pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
pccb->datalen = 16;
- if (scsi_exec(pccb) != TRUE)
+ if (scsi_exec(pccb) != true)
return 1;
*capacity = ((uint64_t)pccb->pdata[0] << 56) |
MORECORE_FAILURE (default: -1)
The value returned upon failure of MORECORE.
MORECORE_CLEARS (default 1)
- True (1) if the routine mapped to MORECORE zeroes out memory (which
+ true (1) if the routine mapped to MORECORE zeroes out memory (which
holds for sbrk).
DEFAULT_TRIM_THRESHOLD
DEFAULT_TOP_PAD
MORECORE_FAILURE (default: -1)
The value returned upon failure of MORECORE.
MORECORE_CLEARS (default 1)
- True (1) if the routine mapped to MORECORE zeroes out memory (which
+ true (1) if the routine mapped to MORECORE zeroes out memory (which
holds for sbrk).
DEFAULT_TRIM_THRESHOLD
DEFAULT_TOP_PAD
/* Length of the BIOS image */
#define MAX_BIOSLEN (128 * 1024L)
-/* Define some useful types and macros */
-#define true 1
-#define false 0
-
/* Place to save PCI BAR's that we change and later restore */
static u32 saveROMBaseAddress;
static u32 saveBaseAddress10;
VGAInfo - BIOS emulator VGA info structure
RETURNS:
-True if successfully initialised, false if not.
+true if successfully initialised, false if not.
REMARKS:
Loads and POST's the display controllers BIOS, directly from the BIOS
PARAMETERS:
pcidev - PCI device info for the video card on the bus to boot
pVGAInfo - Place to return VGA info structure is requested
-cleanUp - True to clean up on exit, false to leave emulator active
+cleanUp - true to clean up on exit, false to leave emulator active
REMARKS:
Boots the PCI/AGP video card on the bus using the Video ROM BIOS image
busmem_base - Base of the VGA bus memory
timer - Timer used to emulate PC timer ports
timer0 - Latched value for timer 0
-timer0Latched - True if timer 0 value was just latched
+timer0Latched - true if timer 0 value was just latched
timer2 - Current value for timer 2
-emulateVGA - True to emulate VGA I/O and memory accesses
+emulateVGA - true to emulate VGA I/O and memory accesses
****************************************************************************/
typedef struct {
case 'P':
noDecode = (noDecode) ? 0 : 1;
printk("Toggled decoding to %s\n",
- (noDecode) ? "FALSE" : "TRUE");
+ (noDecode) ? "false" : "true");
break;
case 't':
case 0:
break;
default:
printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
- return FALSE;
+ return false;
}
if (ret) {
debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
if (status == 0x7f) {
printf("Hard Disk not found.\n");
dev_state = SATA_NODEVICE;
- rc = FALSE;
+ rc = false;
return rc;
}
printf("** TimeOUT **\n");
dev_state = SATA_NODEVICE;
- rc = FALSE;
+ rc = false;
return rc;
}
if ((i >= 100) && ((i % 100) == 0))
} else {
printf("No device found\n");
dev_state = SATA_NODEVICE;
- return FALSE;
+ return false;
}
tmp = ATA_DEVICE_OBS;
status = ata_busy_wait(ap, ATA_BUSY, 30000);
if (status & ATA_BUSY) {
printf("BSY = 0 check. timeout.\n");
- rc = FALSE;
+ rc = false;
return rc;
}
status = ata_busy_wait(ap, ATA_BUSY, 300000);
if (status & ATA_BUSY) {
printf("BSY = 0 check. timeout.\n");
- rc = FALSE;
+ rc = false;
return rc;
}
tag = ATA_TAG_INTERNAL;
if (test_and_set_bit(tag, &ap->qc_allocated)) {
- rc = FALSE;
+ rc = false;
return rc;
}
ret = ata_dev_read_sectors(pdata, datalen, 0, 1);
- if (ret == TRUE)
+ if (ret == true)
break;
i++;
if (i > (ATA_RESET_TIME * 100)) {
printf("** TimeOUT **\n");
dev_state = SATA_NODEVICE;
- return FALSE;
+ return false;
}
if ((i >= 100) && ((i % 100) == 0))
dev_state = SATA_READY;
- return TRUE;
+ return true;
}
static unsigned int ata_dev_set_feature(struct ata_device *dev,
blks = 0;
}
- if (ata_dev_read_sectors(pdata, datalen, block, n_block) != TRUE) {
+ if (ata_dev_read_sectors(pdata, datalen, block, n_block) != true) {
printf("sata_dwc : Hard disk read error.\n");
blkcnt -= blks;
break;
int may_fallback = 1;
if (dev_state == SATA_ERROR)
- return FALSE;
+ return false;
ata_dev_select(ap, dev->devno, 1, 1);
goto err_out;
}
- return TRUE;
+ return true;
err_out:
printf("failed to READ SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
- return FALSE;
+ return false;
}
#if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48)
blks = 0;
}
- if (ata_dev_write_sectors(pdata, datalen, block, n_block) != TRUE) {
+ if (ata_dev_write_sectors(pdata, datalen, block, n_block) != true) {
printf("sata_dwc : Hard disk read error.\n");
blkcnt -= blks;
break;
int may_fallback = 1;
if (dev_state == SATA_ERROR)
- return FALSE;
+ return false;
ata_dev_select(ap, dev->devno, 1, 1);
goto err_out;
}
- return TRUE;
+ return true;
err_out:
printf("failed to WRITE SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
- return FALSE;
+ return false;
}
unsigned char *pdata;
};
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
#endif
retry:
scsi_issue(pccb);
if(pccb->contr_stat!=SIR_COMPLETE)
- return FALSE;
+ return false;
if(pccb->status==S_GOOD)
- return TRUE;
+ return true;
if(pccb->status==S_CHECK_COND) { /* check condition */
for(i=0;i<16;i++)
tmpcmd[i]=pccb->cmd[i];
case SENSE_NO_SENSE:
case SENSE_RECOVERED_ERROR:
/* seems to be ok */
- return TRUE;
+ return true;
break;
case SENSE_NOT_READY:
if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) {
/* if device is not in process of becoming ready */
- return FALSE;
+ return false;
break;
} /* else fall through */
case SENSE_UNIT_ATTENTION:
goto retry;
}
PRINTF("Target %d not ready, %d retried\n",pccb->target,retrycnt);
- return FALSE;
+ return false;
default:
- return FALSE;
+ return false;
}
}
PRINTF("Status = %X\n",pccb->status);
- return FALSE;
+ return false;
}
}
/* Establish the initial state */
- (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */
+ (*fn->config) (true, true, cookie); /* Assert nCONFIG */
udelay(2); /* T_cfg > 2us */
return FPGA_FAIL;
}
- (*fn->config) (FALSE, TRUE, cookie); /* Deassert nCONFIG */
+ (*fn->config) (false, true, cookie); /* Deassert nCONFIG */
udelay(2); /* T_cf2st1 < 4us */
/* Wait for nSTATUS to be released (i.e. deasserted) */
i = 8;
do {
/* Deassert the clock */
- (*fn->clk) (FALSE, TRUE, cookie);
+ (*fn->clk) (false, true, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
- (*fn->data) ( (val & 0x01), TRUE, cookie);
+ (*fn->data) ((val & 0x01), true, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
- (*fn->clk) (TRUE, TRUE, cookie);
+ (*fn->clk) (true, true, cookie);
CONFIG_FPGA_DELAY ();
val >>= 1;
i --;
for (i = 0; i < 12; i++) {
CONFIG_FPGA_DELAY ();
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
}
ret_val = FPGA_SUCCESS;
static int altera_validate (Altera_desc * desc, const char *fn)
{
- int ret_val = FALSE;
+ int ret_val = false;
if (desc) {
if ((desc->family > min_altera_type) &&
if ((desc->iface > min_altera_iface_type) &&
(desc->iface < max_altera_iface_type)) {
if (desc->size) {
- ret_val = TRUE;
+ ret_val = true;
} else {
printf ("%s: NULL part size\n", fn);
}
}
/* Establish the initial state */
- (*fn->config) (FALSE, TRUE, cookie); /* De-assert nCONFIG */
+ (*fn->config) (false, true, cookie); /* De-assert nCONFIG */
udelay(100);
- (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */
+ (*fn->config) (true, true, cookie); /* Assert nCONFIG */
udelay(2); /* T_cfg > 2us */
/* Get ready for the burn */
CONFIG_FPGA_DELAY ();
- ret = (*fn->write) (buf, bsize, TRUE, cookie);
+ ret = (*fn->write) (buf, bsize, true, cookie);
if (ret) {
puts ("** Write failed.\n");
(*fn->abort) (cookie);
static int lattice_validate(Lattice_desc *desc, const char *fn)
{
- int ret_val = FALSE;
+ int ret_val = false;
if (desc) {
if ((desc->family > min_lattice_type) &&
if ((desc->iface > min_lattice_iface_type) &&
(desc->iface < max_lattice_iface_type)) {
if (desc->size) {
- ret_val = TRUE;
+ ret_val = true;
} else {
printf("%s: NULL part size\n", fn);
}
}
/* Establish the initial state */
- (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
+ (*fn->pgm) (true, true, cookie); /* Assert the program, commit */
/* Get ready for the burn */
CONFIG_FPGA_DELAY ();
- (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
+ (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
ts = get_timer (0); /* get current time */
/* Now wait for INIT and BUSY to go high */
}
} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
- (*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
- (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->wr) (true, true, cookie); /* Assert write, commit */
+ (*fn->cs) (true, true, cookie); /* Assert chip select, commit */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
/* Load the data */
while (bytecount < bsize) {
/* XXX - do we check for an Ctrl-C press in here ??? */
/* XXX - Check the error bit? */
- (*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
+ (*fn->wdata) (data[bytecount++], true, cookie); /* write the data */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
ts = get_timer (0); /* get current time */
* make sure we aren't busy forever... */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for BUSY to clear.\n");
}
CONFIG_FPGA_DELAY ();
- (*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */
- (*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */
+ (*fn->cs) (false, true, cookie); /* Deassert the chip select */
+ (*fn->wr) (false, true, cookie); /* Deassert the write pin */
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
while ((*fn->done) (cookie) == FPGA_FAIL) {
CONFIG_FPGA_DELAY ();
- (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
printf ("Starting Dump of FPGA Device %d...\n", cookie);
- (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->cs) (true, true, cookie); /* Assert chip select, commit */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
/* dump the data */
while (bytecount < bsize) {
/* XXX - do we check for an Ctrl-C press in here ??? */
- (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
(*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
#endif
}
- (*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */
- (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->cs) (false, false, cookie); /* Deassert the chip select */
+ (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
}
/* Establish the initial state */
- (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
+ (*fn->pgm) (true, true, cookie); /* Assert the program, commit */
/* Wait for INIT state (init low) */
ts = get_timer (0); /* get current time */
/* Get ready for the burn */
CONFIG_FPGA_DELAY ();
- (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
+ (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
ts = get_timer (0); /* get current time */
/* Now wait for INIT to go high */
i = 8;
do {
/* Deassert the clock */
- (*fn->clk) (FALSE, TRUE, cookie);
+ (*fn->clk) (false, true, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
- (*fn->wr) ((val & 0x80), TRUE, cookie);
+ (*fn->wr) ((val & 0x80), true, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
- (*fn->clk) (TRUE, TRUE, cookie);
+ (*fn->clk) (true, true, cookie);
CONFIG_FPGA_DELAY ();
val <<= 1;
i --;
/* now check for done signal */
ts = get_timer (0); /* get current time */
ret_val = FPGA_SUCCESS;
- (*fn->wr) (TRUE, TRUE, cookie);
+ (*fn->wr) (true, true, cookie);
while (! (*fn->done) (cookie)) {
CONFIG_FPGA_DELAY ();
- (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
putc ('*');
}
/* Establish the initial state */
- (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
+ (*fn->pgm) (true, true, cookie); /* Assert the program, commit */
/* Get ready for the burn */
CONFIG_FPGA_DELAY ();
- (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
+ (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
ts = get_timer (0); /* get current time */
/* Now wait for INIT and BUSY to go high */
}
} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
- (*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
- (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->wr) (true, true, cookie); /* Assert write, commit */
+ (*fn->cs) (true, true, cookie); /* Assert chip select, commit */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
/* Load the data */
while (bytecount < bsize) {
/* XXX - do we check for an Ctrl-C press in here ??? */
/* XXX - Check the error bit? */
- (*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
+ (*fn->wdata) (data[bytecount++], true, cookie); /* write the data */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
ts = get_timer (0); /* get current time */
* make sure we aren't busy forever... */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for BUSY to clear.\n");
}
CONFIG_FPGA_DELAY ();
- (*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */
- (*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */
+ (*fn->cs) (false, true, cookie); /* Deassert the chip select */
+ (*fn->wr) (false, true, cookie); /* Deassert the write pin */
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
* make sure we aren't busy forever... */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
printf ("Starting Dump of FPGA Device %d...\n", cookie);
- (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->cs) (true, true, cookie); /* Assert chip select, commit */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
/* dump the data */
while (bytecount < bsize) {
/* XXX - do we check for an Ctrl-C press in here ??? */
- (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
(*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
#endif
}
- (*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */
- (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->cs) (false, false, cookie); /* Deassert the chip select */
+ (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
}
/* Establish the initial state */
- (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
+ (*fn->pgm) (true, true, cookie); /* Assert the program, commit */
/* Wait for INIT state (init low) */
ts = get_timer (0); /* get current time */
/* Get ready for the burn */
CONFIG_FPGA_DELAY ();
- (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
+ (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */
ts = get_timer (0); /* get current time */
/* Now wait for INIT to go high */
/* Load the data */
if(*fn->bwr)
- (*fn->bwr) (data, bsize, TRUE, cookie);
+ (*fn->bwr) (data, bsize, true, cookie);
else {
while (bytecount < bsize) {
i = 8;
do {
/* Deassert the clock */
- (*fn->clk) (FALSE, TRUE, cookie);
+ (*fn->clk) (false, true, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
- (*fn->wr) ((val & 0x80), TRUE, cookie);
+ (*fn->wr) ((val & 0x80), true, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
- (*fn->clk) (TRUE, TRUE, cookie);
+ (*fn->clk) (true, true, cookie);
CONFIG_FPGA_DELAY ();
val <<= 1;
i --;
/* now check for done signal */
ts = get_timer (0); /* get current time */
ret_val = FPGA_SUCCESS;
- (*fn->wr) (TRUE, TRUE, cookie);
+ (*fn->wr) (true, true, cookie);
while (! (*fn->done) (cookie)) {
/* XXX - we should have a check in here somewhere to
* make sure we aren't busy forever... */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
- (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ (*fn->clk) (true, true, cookie); /* Assert the clock pin */
putc ('*');
* There is no maximum value for the pulse width. Check to make
* sure that INIT_B goes low after assertion of PROG_B
*/
- (*fn->pgm) (TRUE, TRUE, cookie);
+ (*fn->pgm) (true, true, cookie);
udelay (10);
ts = get_timer (0);
do {
}
} while (!(*fn->init) (cookie));
- (*fn->pgm) (FALSE, TRUE, cookie);
+ (*fn->pgm) (false, true, cookie);
CONFIG_FPGA_DELAY ();
- (*fn->clk) (TRUE, TRUE, cookie);
+ (*fn->clk) (true, true, cookie);
/*
* Start a timer and wait for INIT_B to go high
}
} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
- (*fn->wr) (TRUE, TRUE, cookie);
- (*fn->cs) (TRUE, TRUE, cookie);
+ (*fn->wr) (true, true, cookie);
+ (*fn->cs) (true, true, cookie);
udelay (10000);
}
#endif
- (*fn->wdata) (data[bytecount++], TRUE, cookie);
+ (*fn->wdata) (data[bytecount++], true, cookie);
CONFIG_FPGA_DELAY ();
/*
* Cycle the clock pin
*/
- (*fn->clk) (FALSE, TRUE, cookie);
+ (*fn->clk) (false, true, cookie);
CONFIG_FPGA_DELAY ();
- (*fn->clk) (TRUE, TRUE, cookie);
+ (*fn->clk) (true, true, cookie);
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
ts = get_timer (0);
* Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
*/
CONFIG_FPGA_DELAY ();
- (*fn->cs) (FALSE, TRUE, cookie);
- (*fn->wr) (FALSE, TRUE, cookie);
+ (*fn->cs) (false, true, cookie);
+ (*fn->wr) (false, true, cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n');
printf ("Starting Dump of FPGA Device %d...\n", cookie);
- (*fn->cs) (TRUE, TRUE, cookie);
- (*fn->clk) (TRUE, TRUE, cookie);
+ (*fn->cs) (true, true, cookie);
+ (*fn->clk) (true, true, cookie);
while (bytecount < bsize) {
#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
/*
* Cycle the clock and read the data
*/
- (*fn->clk) (FALSE, TRUE, cookie);
- (*fn->clk) (TRUE, TRUE, cookie);
+ (*fn->clk) (false, true, cookie);
+ (*fn->clk) (true, true, cookie);
(*fn->rdata) (&(data[bytecount++]), cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
/*
* Deassert CS_B and cycle the clock to deselect the device.
*/
- (*fn->cs) (FALSE, FALSE, cookie);
- (*fn->clk) (FALSE, TRUE, cookie);
- (*fn->clk) (TRUE, TRUE, cookie);
+ (*fn->cs) (false, false, cookie);
+ (*fn->clk) (false, true, cookie);
+ (*fn->clk) (true, true, cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n');
static int xilinx_validate (Xilinx_desc * desc, char *fn)
{
- int ret_val = FALSE;
+ int ret_val = false;
if (desc) {
if ((desc->family > min_xilinx_type) &&
if ((desc->iface > min_xilinx_iface_type) &&
(desc->iface < max_xilinx_iface_type)) {
if (desc->size) {
- ret_val = TRUE;
+ ret_val = true;
} else
printf ("%s: NULL part size\n", fn);
} else
#define DRIVER_NAME "mxc_nand"
-typedef enum {false, true} bool;
-
struct mxc_nand_host {
struct mtd_info mtd;
struct nand_chip *nand;
}
/* wait for the SMI register to become available */
- if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) {
+ if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
return -1;
}
writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi);
/* now wait for the data to be valid */
- if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, TRUE)) {
+ if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, true)) {
val = readl(®s->smi);
printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
__func__, val);
}
/* wait for the SMI register to become available */
- if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) {
+ if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
return -1;
}
#ifndef __ARMADA100_FEC_H__
#define __ARMADA100_FEC_H__
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
#define PORT_NUM 0x0
/* RX & TX descriptor command */
*
* hw - Struct containing variables accessed by shared code
****************************************************************************/
-static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
+static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
{
uint32_t eecd = 0;
DEBUGFUNC();
if (hw->mac_type == e1000_ich8lan)
- return FALSE;
+ return false;
if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
eecd = E1000_READ_REG(hw, EECD);
/* If both bits are set, device is Flash type */
if (eecd == 0x03)
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
/******************************************************************************
eeprom->opcode_bits = 3;
eeprom->address_bits = 6;
eeprom->delay_usec = 50;
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
+ eeprom->use_eerd = false;
+ eeprom->use_eewr = false;
break;
case e1000_82540:
case e1000_82545:
eeprom->word_size = 64;
eeprom->address_bits = 6;
}
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
+ eeprom->use_eerd = false;
+ eeprom->use_eewr = false;
break;
case e1000_82541:
case e1000_82541_rev_2:
eeprom->address_bits = 6;
}
}
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
+ eeprom->use_eerd = false;
+ eeprom->use_eewr = false;
break;
case e1000_82571:
case e1000_82572:
eeprom->page_size = 8;
eeprom->address_bits = 8;
}
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
+ eeprom->use_eerd = false;
+ eeprom->use_eewr = false;
break;
case e1000_82573:
case e1000_82574:
eeprom->page_size = 8;
eeprom->address_bits = 8;
}
- eeprom->use_eerd = TRUE;
- eeprom->use_eewr = TRUE;
- if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
+ eeprom->use_eerd = true;
+ eeprom->use_eewr = true;
+ if (e1000_is_onboard_nvm_eeprom(hw) == false) {
eeprom->type = e1000_eeprom_flash;
eeprom->word_size = 2048;
eeprom->page_size = 8;
eeprom->address_bits = 8;
}
- eeprom->use_eerd = TRUE;
- eeprom->use_eewr = FALSE;
+ eeprom->use_eerd = true;
+ eeprom->use_eewr = false;
break;
/* ich8lan does not support currently. if needed, please
int32_t i = 0;
eeprom->type = e1000_eeprom_ich8;
- eeprom->use_eerd = FALSE;
- eeprom->use_eewr = FALSE;
+ eeprom->use_eerd = false;
+ eeprom->use_eewr = false;
eeprom->word_size = E1000_SHADOW_RAM_WORDS;
uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
ICH_FLASH_GFPREG);
* so as to save time for driver init */
if (hw->eeprom_shadow_ram != NULL) {
for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
- hw->eeprom_shadow_ram[i].modified = FALSE;
+ hw->eeprom_shadow_ram[i].modified = false;
hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
}
}
* directly. In this case, we need to acquire the EEPROM so that
* FW or other port software does not interrupt.
*/
- if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
- hw->eeprom.use_eerd == FALSE) {
+ if (e1000_is_onboard_nvm_eeprom(hw) == true &&
+ hw->eeprom.use_eerd == false) {
/* Prepare the EEPROM for bit-bang reading */
if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
}
/* Eerd register EEPROM access requires no eeprom aquire/release */
- if (eeprom->use_eerd == TRUE)
+ if (eeprom->use_eerd == true)
return e1000_read_eeprom_eerd(hw, offset, words, data);
/* ich8lan does not support currently. if needed, please
if (ret_val)
return ret_val;
- hw->phy_reset_disable = FALSE;
+ hw->phy_reset_disable = false;
}
}
return E1000_SUCCESS;
}
-static boolean_t e1000_is_second_port(struct e1000_hw *hw)
+static bool e1000_is_second_port(struct e1000_hw *hw)
{
switch (hw->mac_type) {
case e1000_80003es2lan:
case e1000_82546:
case e1000_82571:
if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
- return TRUE;
+ return true;
/* Fallthrough */
default:
- return FALSE;
+ return false;
}
}
E1000_WRITE_FLUSH(hw);
/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
- hw->tbi_compatibility_on = FALSE;
+ hw->tbi_compatibility_on = false;
/* Delay to allow any outstanding PCI transactions to complete before
* resetting the device
hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
hw->mac_type == e1000_82541_rev_2
|| hw->mac_type == e1000_82547_rev_2)
- hw->phy_reset_disable = FALSE;
+ hw->phy_reset_disable = false;
return E1000_SUCCESS;
}
****************************************************************************/
static int32_t
-e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
+e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
{
uint32_t phy_ctrl = 0;
int32_t ret_val;
****************************************************************************/
static int32_t
-e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
+e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
{
uint32_t phy_ctrl = 0;
int32_t ret_val;
/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
if (hw->phy_type == e1000_phy_igp) {
/* disable lplu d3 during driver init */
- ret_val = e1000_set_d3_lplu_state(hw, FALSE);
+ ret_val = e1000_set_d3_lplu_state(hw, false);
if (ret_val) {
DEBUGOUT("Error Disabling LPLU D3\n");
return ret_val;
}
/* disable lplu d0 during driver init */
- ret_val = e1000_set_d0_lplu_state(hw, FALSE);
+ ret_val = e1000_set_d0_lplu_state(hw, false);
if (ret_val) {
DEBUGOUT("Error Disabling LPLU D0\n");
return ret_val;
/*****************************************************************************
* This function checks the mode of the firmware.
*
- * returns - TRUE when the mode is IAMT or FALSE.
+ * returns - true when the mode is IAMT or false.
****************************************************************************/
-boolean_t
+bool
e1000_check_mng_mode(struct e1000_hw *hw)
{
uint32_t fwsm;
if (hw->mac_type == e1000_ich8lan) {
if ((fwsm & E1000_FWSM_MODE_MASK) ==
(E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
- return TRUE;
+ return true;
} else if ((fwsm & E1000_FWSM_MODE_MASK) ==
(E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
- return TRUE;
+ return true;
- return FALSE;
+ return false;
}
static int32_t
* firmware will have already initialized them. We only initialize
* them if the HW is not in IAMT mode.
*/
- if (e1000_check_mng_mode(hw) == FALSE) {
+ if (e1000_check_mng_mode(hw) == false) {
/* Enable Electrical Idle on the PHY */
phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
ret_val = e1000_write_phy_reg(hw,
}
}
- hw->get_link_status = TRUE;
+ hw->get_link_status = true;
return E1000_SUCCESS;
}
}
if (phy_data & MII_SR_LINK_STATUS) {
- hw->get_link_status = FALSE;
+ hw->get_link_status = false;
} else {
/* No link detected */
return -E1000_ERR_NOLINK;
rctl = E1000_READ_REG(hw, RCTL);
rctl &= ~E1000_RCTL_SBP;
E1000_WRITE_REG(hw, RCTL, rctl);
- hw->tbi_compatibility_on = FALSE;
+ hw->tbi_compatibility_on = false;
}
} else {
/* If TBI compatibility is was previously off, turn it on. For
* will look like CRC errors to to the hardware.
*/
if (!hw->tbi_compatibility_on) {
- hw->tbi_compatibility_on = TRUE;
+ hw->tbi_compatibility_on = true;
rctl = E1000_READ_REG(hw, RCTL);
rctl |= E1000_RCTL_SBP;
E1000_WRITE_REG(hw, RCTL, rctl);
{
int32_t phy_init_status, ret_val;
uint16_t phy_id_high, phy_id_low;
- boolean_t match = FALSE;
+ bool match = false;
DEBUGFUNC();
switch (hw->mac_type) {
case e1000_82543:
if (hw->phy_id == M88E1000_E_PHY_ID)
- match = TRUE;
+ match = true;
break;
case e1000_82544:
if (hw->phy_id == M88E1000_I_PHY_ID)
- match = TRUE;
+ match = true;
break;
case e1000_82540:
case e1000_82545:
case e1000_82546:
case e1000_82546_rev_3:
if (hw->phy_id == M88E1011_I_PHY_ID)
- match = TRUE;
+ match = true;
break;
case e1000_82541:
case e1000_82541_rev_2:
case e1000_82547:
case e1000_82547_rev_2:
if(hw->phy_id == IGP01E1000_I_PHY_ID)
- match = TRUE;
+ match = true;
break;
case e1000_82573:
if (hw->phy_id == M88E1111_I_PHY_ID)
- match = TRUE;
+ match = true;
break;
case e1000_82574:
if (hw->phy_id == BME1000_E_PHY_ID)
- match = TRUE;
+ match = true;
break;
case e1000_80003es2lan:
if (hw->phy_id == GG82563_E_PHY_ID)
- match = TRUE;
+ match = true;
break;
case e1000_ich8lan:
if (hw->phy_id == IGP03E1000_E_PHY_ID)
- match = TRUE;
+ match = true;
if (hw->phy_id == IFE_E_PHY_ID)
- match = TRUE;
+ match = true;
if (hw->phy_id == IFE_PLUS_E_PHY_ID)
- match = TRUE;
+ match = true;
if (hw->phy_id == IFE_C_E_PHY_ID)
- match = TRUE;
+ match = true;
break;
default:
DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
if (hw->mac_type != e1000_82543) {
/* tbi_compatibility is only valid on 82543 */
- hw->tbi_compatibility_en = FALSE;
+ hw->tbi_compatibility_en = false;
}
switch (hw->device_id) {
if (status & E1000_STATUS_TBIMODE) {
hw->media_type = e1000_media_type_fiber;
/* tbi_compatibility not valid on fiber */
- hw->tbi_compatibility_en = FALSE;
+ hw->tbi_compatibility_en = false;
} else {
hw->media_type = e1000_media_type_copper;
}
hw->media_type = e1000_media_type_fiber;
}
- hw->tbi_compatibility_en = TRUE;
- hw->wait_autoneg_complete = TRUE;
+ hw->tbi_compatibility_en = true;
+ hw->wait_autoneg_complete = true;
if (hw->mac_type < e1000_82543)
hw->report_tx_early = 0;
else
hw->original_fc = e1000_fc_default;
hw->autoneg_failed = 0;
hw->autoneg = 1;
- hw->get_link_status = TRUE;
+ hw->get_link_status = true;
hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
PCI_REGION_MEM);
hw->mac_type = e1000_undefined;
int argc, char * const argv[]);
#endif
-typedef enum {
- FALSE = 0,
- TRUE = 1
-} boolean_t;
-
/* Enumerated types specific to the e1000 hardware */
/* Media Access Controlers */
typedef enum {
Control and Address */
#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special
control register */
-#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False
+#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive false
Carrier Counter */
#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet
Counter */
};
struct e1000_eeprom_info {
- e1000_eeprom_type type;
- uint16_t word_size;
- uint16_t opcode_bits;
- uint16_t address_bits;
- uint16_t delay_usec;
- uint16_t page_size;
- boolean_t use_eerd;
- boolean_t use_eewr;
+e1000_eeprom_type type;
+ uint16_t word_size;
+ uint16_t opcode_bits;
+ uint16_t address_bits;
+ uint16_t delay_usec;
+ uint16_t page_size;
+ bool use_eerd;
+ bool use_eewr;
};
typedef enum {
#if 0
uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
#endif
- boolean_t disable_polarity_correction;
- boolean_t speed_downgraded;
- boolean_t get_link_status;
- boolean_t tbi_compatibility_en;
- boolean_t tbi_compatibility_on;
- boolean_t fc_strict_ieee;
- boolean_t fc_send_xon;
- boolean_t report_tx_early;
- boolean_t phy_reset_disable;
- boolean_t initialize_hw_bits_disable;
+ bool disable_polarity_correction;
+ bool speed_downgraded;
+ bool get_link_status;
+ bool tbi_compatibility_en;
+ bool tbi_compatibility_on;
+ bool fc_strict_ieee;
+ bool fc_send_xon;
+ bool report_tx_early;
+ bool phy_reset_disable;
+ bool initialize_hw_bits_disable;
#if 0
- boolean_t adaptive_ifs;
- boolean_t ifs_params_forced;
- boolean_t in_ifs_mode;
+ bool adaptive_ifs;
+ bool ifs_params_forced;
+ bool in_ifs_mode;
#endif
e1000_smart_speed smart_speed;
e1000_dsp_config dsp_config_state;
* Typical use:
* ...
* if (TBI_ACCEPT) {
- * accept_frame = TRUE;
+ * accept_frame = true;
* e1000_tbi_adjust_stats(adapter, MacAddress);
* frame_length--;
* } else {
- * accept_frame = FALSE;
+ * accept_frame = false;
* }
* ...
*/
#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
-#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */
+#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=false Carrier */
#define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
#define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
#define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
* never return an error.
*/
static int e1000_spi_xfer(struct e1000_hw *hw, unsigned int bitlen,
- const void *dout_mem, void *din_mem, boolean_t intr)
+ const void *dout_mem, void *din_mem, bool intr)
{
const uint8_t *dout = dout_mem;
uint8_t *din = din_mem;
if (flags & SPI_XFER_BEGIN)
e1000_standby_eeprom(hw);
- ret = e1000_spi_xfer(hw, bitlen, dout_mem, din_mem, TRUE);
+ ret = e1000_spi_xfer(hw, bitlen, dout_mem, din_mem, true);
if (flags & SPI_XFER_END)
e1000_standby_eeprom(hw);
#define SPI_EEPROM_STATUS_BUSY 0x01
#define SPI_EEPROM_STATUS_WREN 0x02
-static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, boolean_t intr)
+static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, bool intr)
{
u8 op[] = { SPI_EEPROM_ENABLE_WR };
e1000_standby_eeprom(hw);
* of the EEPROM commands at this time.
*/
#if 0
-static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, boolean_t intr)
+static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, bool intr)
{
u8 op[] = { SPI_EEPROM_DISABLE_WR };
e1000_standby_eeprom(hw);
}
static int e1000_spi_eeprom_write_status(struct e1000_hw *hw,
- u8 status, boolean_t intr)
+ u8 status, bool intr)
{
u8 op[] = { SPI_EEPROM_WRITE_STATUS, status };
e1000_standby_eeprom(hw);
}
#endif
-static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, boolean_t intr)
+static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, bool intr)
{
u8 op[] = { SPI_EEPROM_READ_STATUS, 0 };
e1000_standby_eeprom(hw);
}
static int e1000_spi_eeprom_write_page(struct e1000_hw *hw,
- const void *data, u16 off, u16 len, boolean_t intr)
+ const void *data, u16 off, u16 len, bool intr)
{
u8 op[] = {
SPI_EEPROM_WRITE_PAGE,
}
static int e1000_spi_eeprom_read_page(struct e1000_hw *hw,
- void *data, u16 off, u16 len, boolean_t intr)
+ void *data, u16 off, u16 len, bool intr)
{
u8 op[] = {
SPI_EEPROM_READ_PAGE,
return 0;
}
-static int e1000_spi_eeprom_poll_ready(struct e1000_hw *hw, boolean_t intr)
+static int e1000_spi_eeprom_poll_ready(struct e1000_hw *hw, bool intr)
{
int status;
while ((status = e1000_spi_eeprom_read_status(hw, intr)) >= 0) {
}
static int e1000_spi_eeprom_dump(struct e1000_hw *hw,
- void *data, u16 off, unsigned int len, boolean_t intr)
+ void *data, u16 off, unsigned int len, bool intr)
{
/* Interruptibly wait for the EEPROM to be ready */
if (e1000_spi_eeprom_poll_ready(hw, intr))
}
static int e1000_spi_eeprom_program(struct e1000_hw *hw,
- const void *data, u16 off, u16 len, boolean_t intr)
+ const void *data, u16 off, u16 len, bool intr)
{
/* Program each page in sequence */
while (len) {
free(buffer);
return 1;
}
- err = e1000_spi_eeprom_dump(hw, buffer, offset, length, TRUE);
+ err = e1000_spi_eeprom_dump(hw, buffer, offset, length, true);
e1000_release_eeprom(hw);
if (err) {
E1000_ERR(hw->nic, "Interrupted!\n");
}
/* Perform the programming operation */
- if (e1000_spi_eeprom_dump(hw, dest, offset, length, TRUE) < 0) {
+ if (e1000_spi_eeprom_dump(hw, dest, offset, length, true) < 0) {
E1000_ERR(hw->nic, "Interrupted!\n");
e1000_release_eeprom(hw);
return 1;
}
/* Perform the programming operation */
- if (e1000_spi_eeprom_program(hw, source, offset, length, TRUE) < 0) {
+ if (e1000_spi_eeprom_program(hw, source, offset, length, true) < 0) {
E1000_ERR(hw->nic, "Interrupted!\n");
e1000_release_eeprom(hw);
return 1;
{
uint16_t i, length, checksum = 0, checksum_reg;
uint16_t *buffer;
- boolean_t upd;
+ bool upd;
if (argc == 0)
upd = 0;
}
/* Read the EEPROM */
- if (e1000_spi_eeprom_dump(hw, buffer, 0, length, TRUE) < 0) {
+ if (e1000_spi_eeprom_dump(hw, buffer, 0, length, true) < 0) {
E1000_ERR(hw->nic, "Interrupted!\n");
e1000_release_eeprom(hw);
return 1;
printf("%s: Reprogramming the EEPROM checksum...\n", hw->nic->name);
buffer[i] = cpu_to_le16(checksum);
if (e1000_spi_eeprom_program(hw, &buffer[i], i * sizeof(uint16_t),
- sizeof(uint16_t), TRUE)) {
+ sizeof(uint16_t), true)) {
E1000_ERR(hw->nic, "Interrupted!\n");
e1000_release_eeprom(hw);
return 1;
#ifndef __NE2000_BASE_H__
#define __NE2000_BASE_H__
-#define bool int
-#define false 0
-#define true 1
-
/*
* Debugging details
*
* @ingroup IxEthAccPri
*
*/
-BOOL ixEthAccServiceInit = FALSE;
+BOOL ixEthAccServiceInit = false;
/* global filtering bit mask */
PUBLIC UINT32 ixEthAccNewSrcMask;
}
/* initialiasation is complete */
- ixEthAccServiceInit = TRUE;
+ ixEthAccServiceInit = true;
return IX_ETH_ACC_SUCCESS;
/* set all ports as uninitialized */
for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
{
- ixEthAccPortData[portId].portInitialized = FALSE;
+ ixEthAccPortData[portId].portInitialized = false;
}
/* uninitialize the service */
- ixEthAccServiceInit = FALSE;
+ ixEthAccServiceInit = false;
}
}
* Set the port init flag.
*/
- ixEthAccPortData[portId].portInitialized = TRUE;
+ ixEthAccPortData[portId].portInitialized = true;
#ifdef CONFIG_IXP425_COMPONENT_ETHDB
/* init learning/filtering database structures for this port */
(IxQMgrCallbackId) 0, /**< Callback tag */
IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- TRUE, /**< Enable Q notification at startup */
+ true, /**< Enable Q notification at startup */
IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */
IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */
(IxQMgrCallbackId) 0, /**< Callback tag */
IX_QMGR_Q_SIZE64, /**< Allocate Smaller Q */
IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- TRUE, /**< Enable Q notification at startup */
+ true, /**< Enable Q notification at startup */
IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */
IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */
(IxQMgrCallbackId) IX_ETH_PORT_1,
IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- FALSE, /**< Disable Q notification at startup */
+ false, /**< Disable Q notification at startup */
IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback */
IX_QMGR_Q_WM_LEVEL0, /***< Q Low water mark */
IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
(IxQMgrCallbackId) IX_ETH_PORT_2,
IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- FALSE, /**< Disable Q notification at startup */
+ false, /**< Disable Q notification at startup */
IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE, /**< Q Condition to drive callback */
IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
(IxQMgrCallbackId) IX_ETH_PORT_3,
IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- FALSE, /**< Disable Q notification at startup */
+ false, /**< Disable Q notification at startup */
IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE, /**< Q Condition to drive callback */
IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
(IxQMgrCallbackId) IX_ETH_PORT_1,
IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- FALSE, /**< Disable Q notification at startup */
+ false, /**< Disable Q notification at startup */
IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE, /**< Q Condition to drive callback */
IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
(IxQMgrCallbackId) IX_ETH_PORT_2,
IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- FALSE, /**< Disable Q notification at startup */
+ false, /**< Disable Q notification at startup */
IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE, /**< Q Condition to drive callback */
IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
(IxQMgrCallbackId) IX_ETH_PORT_3,
IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
IX_QMGR_Q_ENTRY_SIZE1, /** Queue Entry Sizes - all Q entries are single ord entries */
- FALSE, /** Disable Q notification at startup */
+ false, /** Disable Q notification at startup */
IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE, /** Q Condition to drive callback */
IX_QMGR_Q_WM_LEVEL0, /* No queues use almost empty */
IX_QMGR_Q_WM_LEVEL64, /** Q High water mark - needed used */
(IxQMgrCallbackId) 0,
IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- TRUE, /**< Enable Q notification at startup */
+ true, /**< Enable Q notification at startup */
IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback */
IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
IX_QMGR_Q_WM_LEVEL2, /**< Q High water mark - needed by NPE */
/*
* Set notification condition for Q
*/
- if ( qInfoDes->qNotificationEnableAtStartup == TRUE )
+ if (qInfoDes->qNotificationEnableAtStartup == true)
{
if ( ixQMgrNotificationEnable(qInfoDes->qId,
qInfoDes->qConditionSource)
IxEthDBProperty ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
IxEthDBPropertyType ixEthDBPropertyType = IX_ETH_DB_INTEGER_PROPERTY;
UINT32 ixEthDBParameter = 0;
- BOOL completelySorted = FALSE;
+ BOOL completelySorted = false;
/* Fill the corspondance between ports and queues
* This defines the mapping from port to queue Ids.
do
{
sortIterations++;
- completelySorted = TRUE;
+ completelySorted = true;
for (rxQueue = 0;
rxQueue < rxQueueCount - sortIterations;
rxQueue++)
rxQueues[rxQueue+1].npeId = npeId;
rxQueues[rxQueue+1].qId = qId;
rxQueues[rxQueue+1].trafficClass = trafficClass;
- completelySorted = FALSE;
+ completelySorted = false;
}
}
}
for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
{
if ((ixEthAccMacState[port].portDisableState == ACTIVE)
- && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == TRUE))
+ && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == true))
{
/* one of the active ports has a different rx callback type.
* Changing the callback type when the port is enabled
return (IX_ETH_ACC_INVALID_ARG);
}
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = FALSE;
+ ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = false;
return (IX_ETH_ACC_SUCCESS);
}
for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
{
if ((ixEthAccMacState[port].portDisableState == ACTIVE)
- && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == FALSE))
+ && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == false))
{
/* one of the active ports has a different rx callback type.
* Changing the callback type when the port is enabled
return (IX_ETH_ACC_INVALID_ARG);
}
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = TRUE;
+ ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = true;
return (IX_ETH_ACC_SUCCESS);
}
IX_ETH_ACC_FATAL_LOG(
"ixEthRxFrameProcess: Illegal port: %u\n",
(UINT32)portId, 0, 0, 0, 0, 0);
- return FALSE;
+ return false;
}
#endif
if ((flags & (IX_ETHACC_NE_FILTERMASK | IX_ETHACC_NE_NEWSRCMASK)) == 0)
{
/* "best case" scenario : nothing special to do for this frame */
- return TRUE;
+ return true;
}
#ifdef CONFIG_IXP425_COMPONENT_ETHDB
RX_STATS_INC(portId, rxFiltered);
/* indicate that frame should not be subjected to further processing */
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
/* set the global state */
ixEthAccMacState[portId].portDisableState = ACTIVE;
- ixEthAccMacState[portId].enabled = TRUE;
+ ixEthAccMacState[portId].enabled = true;
/* rewrite the setup (including mac filtering) depending
* on current options
IxEthAccPortId portId = (IxEthAccPortId)cbTag;
/* call the portDisable receive callback */
- (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, FALSE);
+ (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, false);
}
PRIVATE void
while (*mBufPtr)
{
/* call the portDisable receive callback with one buffer at a time */
- (ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, TRUE);
+ (ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, true);
}
}
}
/* disable MAC Tx and Rx services */
- ixEthAccMacState[portId].enabled = FALSE;
+ ixEthAccMacState[portId].enabled = false;
ixEthAccMacStateUpdate(portId);
/* restore the Rx and TxDone callbacks (within a critical section) */
IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0);
/* Since Eth NPE is not available, port must be disabled */
- *enabled = FALSE ;
+ *enabled = false ;
return IX_ETH_ACC_SUCCESS ;
}
if (!IX_ETH_IS_PORT_INITIALIZED(portId))
{
/* Since Eth NPE is not available, port must be disabled */
- *enabled = FALSE ;
+ *enabled = false ;
return (IX_ETH_ACC_PORT_UNINITIALIZED);
}
IX_ETH_ACC_MAC_RX_CNTRL1,
regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN);
- ixEthAccMacState[portId].promiscuous = FALSE;
+ ixEthAccMacState[portId].promiscuous = false;
ixEthAccMulticastAddressSet(portId);
IX_ETH_ACC_MAC_RX_CNTRL1,
regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN);
- ixEthAccMacState[portId].promiscuous = TRUE;
+ ixEthAccMacState[portId].promiscuous = true;
ixEthAccMulticastAddressSet(portId);
IX_ETH_ACC_MAC_UNI_ADDR_1 + i*sizeof(UINT32),
macAddr->macAddress[i]);
}
- ixEthAccMacState[portId].initDone = TRUE;
+ ixEthAccMacState[portId].initDone = true;
return IX_ETH_ACC_SUCCESS;
}
IX_IEEE803_MAC_ADDRESS_SIZE);
ixEthAccMacState[portId].mcastAddrIndex = 1;
- ixEthAccMacState[portId].joinAll = TRUE;
+ ixEthAccMacState[portId].joinAll = true;
ixEthAccMulticastAddressSet(portId);
{
if(ixEthAccMacEqual(macAddr, &mcastMacAddr))
{
- ixEthAccMacState[portId].joinAll = FALSE;
+ ixEthAccMacState[portId].joinAll = false;
}
/*Decrement the index into the multicast address table
for the current port*/
}
ixEthAccMacState[portId].mcastAddrIndex = 0;
- ixEthAccMacState[portId].joinAll = FALSE;
+ ixEthAccMacState[portId].joinAll = false;
ixEthAccMulticastAddressSet(portId);
REG_WRITE(ixEthAccMacBase[portId],
IX_ETH_ACC_MAC_RX_CNTRL1,
rxregval | IX_ETH_ACC_RX_CNTRL1_PAUSE_EN);
- ixEthAccMacState[portId].fullDuplex = TRUE;
+ ixEthAccMacState[portId].fullDuplex = true;
}
else if (mode == IX_ETH_ACC_HALF_DUPLEX)
IX_ETH_ACC_MAC_RX_CNTRL1,
rxregval & ~IX_ETH_ACC_RX_CNTRL1_PAUSE_EN);
- ixEthAccMacState[portId].fullDuplex = FALSE;
+ ixEthAccMacState[portId].fullDuplex = false;
}
else
{
regval |
IX_ETH_ACC_TX_CNTRL1_PAD_EN);
- ixEthAccMacState[portId].txPADAppend = TRUE;
+ ixEthAccMacState[portId].txPADAppend = true;
return IX_ETH_ACC_SUCCESS;
}
IX_ETH_ACC_MAC_TX_CNTRL1,
regval & ~IX_ETH_ACC_TX_CNTRL1_PAD_EN);
- ixEthAccMacState[portId].txPADAppend = FALSE;
+ ixEthAccMacState[portId].txPADAppend = false;
return IX_ETH_ACC_SUCCESS;
}
IX_ETH_ACC_MAC_TX_CNTRL1,
regval | IX_ETH_ACC_TX_CNTRL1_FCS_EN);
- ixEthAccMacState[portId].txFCSAppend = TRUE;
+ ixEthAccMacState[portId].txFCSAppend = true;
return IX_ETH_ACC_SUCCESS;
}
IX_ETH_ACC_MAC_TX_CNTRL1,
regval & ~IX_ETH_ACC_TX_CNTRL1_FCS_EN);
- ixEthAccMacState[portId].txFCSAppend = FALSE;
+ ixEthAccMacState[portId].txFCSAppend = false;
return IX_ETH_ACC_SUCCESS;
}
IX_ETH_ACC_MAC_RX_CNTRL1,
regval | IX_ETH_ACC_RX_CNTRL1_CRC_EN);
- ixEthAccMacState[portId].rxFCSAppend = TRUE;
+ ixEthAccMacState[portId].rxFCSAppend = true;
return IX_ETH_ACC_SUCCESS;
}
IX_ETH_ACC_MAC_RX_CNTRL1,
regval & ~IX_ETH_ACC_RX_CNTRL1_CRC_EN);
- ixEthAccMacState[portId].rxFCSAppend = FALSE;
+ ixEthAccMacState[portId].rxFCSAppend = false;
return IX_ETH_ACC_SUCCESS;
}
return IX_ETH_ACC_SUCCESS ;
}
- if(ixEthAccMacState[portId].macInitialised == FALSE)
+ if(ixEthAccMacState[portId].macInitialised == false)
{
- ixEthAccMacState[portId].fullDuplex = TRUE;
- ixEthAccMacState[portId].rxFCSAppend = TRUE;
- ixEthAccMacState[portId].txFCSAppend = TRUE;
- ixEthAccMacState[portId].txPADAppend = TRUE;
- ixEthAccMacState[portId].enabled = FALSE;
- ixEthAccMacState[portId].promiscuous = TRUE;
- ixEthAccMacState[portId].joinAll = FALSE;
- ixEthAccMacState[portId].initDone = FALSE;
- ixEthAccMacState[portId].macInitialised = TRUE;
+ ixEthAccMacState[portId].fullDuplex = true;
+ ixEthAccMacState[portId].rxFCSAppend = true;
+ ixEthAccMacState[portId].txFCSAppend = true;
+ ixEthAccMacState[portId].txPADAppend = true;
+ ixEthAccMacState[portId].enabled = false;
+ ixEthAccMacState[portId].promiscuous = true;
+ ixEthAccMacState[portId].joinAll = false;
+ ixEthAccMacState[portId].initDone = false;
+ ixEthAccMacState[portId].macInitialised = true;
/* initialize MIB stats mutexes */
ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsLock);
{
UINT32 regval;
- if ( ixEthAccMacState[portId].enabled == FALSE )
+ if ( ixEthAccMacState[portId].enabled == false )
{
/* Just disable both the transmitter and reciver in the MAC. */
REG_READ(ixEthAccMacBase[portId],
ixEthAccPortPromiscuousModeClearPriv(portId);
}
- if ( ixEthAccMacState[portId].enabled == TRUE )
+ if ( ixEthAccMacState[portId].enabled == true )
{
/* Enable both the transmitter and reciver in the MAC. */
REG_READ(ixEthAccMacBase[portId],
{
if(macAddr1->macAddress[i] != macAddr2->macAddress[i])
{
- return FALSE;
+ return false;
}
}
- return TRUE;
+ return true;
}
PRIVATE void
* are set in the result
*/
- if (ixEthAccMacState[portId].promiscuous == TRUE)
+ if (ixEthAccMacState[portId].promiscuous == true)
{
/* Promiscuous Mode is set, and filtering
* allow all packets, and enable the mcast and
}
else
{
- if(ixEthAccMacState[portId].joinAll == TRUE)
+ if(ixEthAccMacState[portId].joinAll == true)
{
/* Join all is set. The mask and address are
* the multicast settings.
IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
- return ixEthDBTriggerAddPortUpdate(macAddr, portID, TRUE);
+ return ixEthDBTriggerAddPortUpdate(macAddr, portID, true);
}
IX_ETH_DB_PUBLIC
IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
- return ixEthDBTriggerAddPortUpdate(macAddr, portID, FALSE);
+ return ixEthDBTriggerAddPortUpdate(macAddr, portID, false);
}
IX_ETH_DB_PUBLIC
{
HashIterator iterator;
UINT32 portIndex;
- BOOL agingRequired = FALSE;
+ BOOL agingRequired = false;
/* ports who will have deleted records and therefore will need updating */
IxEthDBPortMap triggerPorts;
{
if (ixEthDBPortInfo[portIndex].agingEnabled && ixEthDBPortInfo[portIndex].enabled)
{
- agingRequired = TRUE;
+ agingRequired = true;
}
}
}
else
{
- ixEthDBPortInfo[portIndex].agingEnabled = FALSE;
- ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = FALSE;
- ixEthDBPortInfo[portIndex].updateMethod.userControlled = TRUE;
+ ixEthDBPortInfo[portIndex].agingEnabled = false;
+ ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false;
+ ixEthDBPortInfo[portIndex].updateMethod.userControlled = true;
ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
IX_OSAL_LOG_DEV_STDOUT,
{
MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
UINT32 *age = NULL;
- BOOL staticEntry = TRUE;
+ BOOL staticEntry = true;
if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
{
}
else
{
- staticEntry = TRUE;
+ staticEntry = true;
}
- if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == FALSE))
+ if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == false))
{
/* manually increment the age if the port has no such capability */
if ((ixEthDBPortDefinitions[descriptor->portID].capabilities & IX_ETH_ENTRY_AGING) == 0)
IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
- ixEthDBPortInfo[portID].agingEnabled = FALSE;
+ ixEthDBPortInfo[portID].agingEnabled = false;
return IX_ETH_DB_SUCCESS;
}
IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
- ixEthDBPortInfo[portID].agingEnabled = TRUE;
+ ixEthDBPortInfo[portID].agingEnabled = true;
return IX_ETH_DB_SUCCESS;
}
IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
ixEthDBPortInfo[portID].updateMethod.updateEnabled = enableUpdate;
- ixEthDBPortInfo[portID].updateMethod.userControlled = TRUE;
+ ixEthDBPortInfo[portID].updateMethod.userControlled = true;
return IX_ETH_DB_SUCCESS;
}
SET_DEPENDENCY_MAP(portInfo->dependencyPortMap, portID);
/* default values */
- portInfo->agingEnabled = FALSE;
- portInfo->enabled = FALSE;
- portInfo->macAddressUploaded = FALSE;
+ portInfo->agingEnabled = false;
+ portInfo->enabled = false;
+ portInfo->macAddressUploaded = false;
portInfo->maxRxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE;
portInfo->maxTxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE;
/* default update control values */
portInfo->updateMethod.searchTree = NULL;
- portInfo->updateMethod.searchTreePendingWrite = FALSE;
- portInfo->updateMethod.treeInitialized = FALSE;
- portInfo->updateMethod.updateEnabled = FALSE;
- portInfo->updateMethod.userControlled = FALSE;
+ portInfo->updateMethod.searchTreePendingWrite = false;
+ portInfo->updateMethod.treeInitialized = false;
+ portInfo->updateMethod.updateEnabled = false;
+ portInfo->updateMethod.userControlled = false;
/* default WiFi parameters */
memset(portInfo->bbsid, 0, sizeof (portInfo->bbsid));
}
/* initialize state save */
- ixEthDBPortState[portID].saved = FALSE;
+ ixEthDBPortState[portID].saved = false;
- portInfo->initialized = TRUE;
+ portInfo->initialized = true;
}
/**
SET_DEPENDENCY_MAP(triggerPorts, portID);
/* mark as enabled */
- portInfo->enabled = TRUE;
+ portInfo->enabled = true;
/* Operation stops here when Ethernet Learning is not enabled */
if(IX_FEATURE_CTRL_SWCONFIG_DISABLED ==
if (!portInfo->updateMethod.userControlled
&& ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0))
{
- portInfo->updateMethod.updateEnabled = TRUE;
+ portInfo->updateMethod.updateEnabled = true;
}
/* if this is first time initialization then we already have
ixEthDBUpdatePortLearningTrees(triggerPorts);
/* mark tree as being initialized */
- portInfo->updateMethod.treeInitialized = TRUE;
+ portInfo->updateMethod.treeInitialized = true;
}
}
ixEthDBFilteringPortMaximumTxFrameSizeSet(portID, ixEthDBPortState[portID].maxTxFrameSize);
/* discard previous save */
- ixEthDBPortState[portID].saved = FALSE;
+ ixEthDBPortState[portID].saved = false;
}
IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Enabling succeeded for port %d\n", portID);
memcpy(ixEthDBPortState[portID].transmitTaggingInfo, portInfo->transmitTaggingInfo, sizeof (IxEthDBVlanSet));
memcpy(ixEthDBPortState[portID].priorityTable, portInfo->priorityTable, sizeof (IxEthDBPriorityTable));
- ixEthDBPortState[portID].saved = TRUE;
+ ixEthDBPortState[portID].saved = true;
/* now turn off all EthDB filtering features on the port */
if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
{
ixEthDBPortVlanMembershipRangeAdd((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID);
- ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, FALSE);
+ ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, false);
ixEthDBAcceptableFrameTypeSet((IxEthDBPortId) portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
ixEthDBIngressVlanTaggingEnabledSet((IxEthDBPortId) portID, IX_ETH_DB_PASS_THROUGH);
/* STP */
if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
{
- ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, FALSE);
+ ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, false);
}
/* Firewall */
{
ixEthDBFirewallModeSet((IxEthDBPortId) portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
ixEthDBFirewallTableDownload((IxEthDBPortId) portID);
- ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, FALSE);
+ ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, false);
}
/* Frame size filter */
}
/* mark as disabled */
- portInfo->enabled = FALSE;
+ portInfo->enabled = false;
/* disable updates unless the user has specifically altered the default behavior */
if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
{
if (!portInfo->updateMethod.userControlled)
{
- portInfo->updateMethod.updateEnabled = FALSE;
+ portInfo->updateMethod.updateEnabled = false;
}
/* make sure we re-initialize the NPE learning tree when the port is re-enabled */
- portInfo->updateMethod.treeInitialized = FALSE;
+ portInfo->updateMethod.treeInitialized = false;
}
ixEthDBUpdateUnlock();
if (result == IX_SUCCESS)
{
- ixEthDBPortInfo[portID].macAddressUploaded = TRUE;
+ ixEthDBPortInfo[portID].macAddressUploaded = true;
}
return result;
IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyType[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
/* private initialization flag */
-IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = FALSE;
+IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = false;
/**
* @brief initializes EthDB
ixEthDBFeatureCapabilityScan();
}
- ethDBInitializationComplete = TRUE;
+ ethDBInitializationComplete = true;
return result;
}
ixOsalMutexDestroy(&ixEthDBPortInfo[portIndex].npeAckLock);
}
- ixEthDBPortInfo[portIndex].initialized = FALSE;
+ ixEthDBPortInfo[portIndex].initialized = false;
}
/* shutdown event processor */
/* deallocate NPE update zones */
ixEthDBNPEUpdateAreasUnload();
- ethDBInitializationComplete = FALSE;
+ ethDBInitializationComplete = false;
return IX_ETH_DB_SUCCESS;
}
IX_ETH_DB_PRIVATE IxOsalMutex eventQueueLock;
IX_ETH_DB_PRIVATE IxOsalMutex portUpdateLock;
-IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown = FALSE;
-IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = FALSE;
+IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown = false;
+IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = false;
/* imported data */
extern HashTable dbHashtable;
return IX_ETH_DB_FAIL;
}
- ixEthDBLearningShutdown = FALSE;
+ ixEthDBLearningShutdown = false;
/* create processor loop thread */
if (ixOsalThreadCreate(&eventProcessorThread, &threadAttr, ixEthDBEventProcessorLoop, NULL) != IX_SUCCESS)
IX_ETH_DB_PUBLIC
IxEthDBStatus ixEthDBStopLearningFunction(void)
{
- ixEthDBLearningShutdown = TRUE;
+ ixEthDBLearningShutdown = true;
/* wake up event processing loop to actually process the shutdown event */
ixOsalSemaphorePost(&eventQueueSemaphore);
IxEthDBPortMap triggerPorts;
IxEthDBPortId portIndex;
- ixEthDBEventProcessorRunning = TRUE;
+ ixEthDBEventProcessorRunning = true;
IX_ETH_DB_EVENTS_TRACE("DB: (Events) Event processor loop was started\n");
while (!ixEthDBLearningShutdown)
{
- BOOL keepProcessing = TRUE;
+ BOOL keepProcessing = true;
UINT32 processedEvents = 0;
IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Waiting for new learning event...\n");
if (processedEvents > EVENT_PROCESSING_LIMIT /* maximum burst reached? */
|| ixOsalSemaphoreTryWait(&eventQueueSemaphore) != IX_SUCCESS) /* or empty queue? */
{
- keepProcessing = FALSE;
+ keepProcessing = false;
}
}
/* turn off automatic updates */
for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
{
- ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = FALSE;
+ ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false;
}
- ixEthDBEventProcessorRunning = FALSE;
+ ixEthDBEventProcessorRunning = false;
}
/**
*
* @param macAddr MAC address of the new record
* @param portID port ID of the new record
- * @param staticEntry TRUE if record is static, FALSE if dynamic
+ * @param staticEntry true if record is static, false if dynamic
*
* @return IX_ETH_DB_SUCCESS if the event creation was
* successfull or IX_ETH_DB_BUSY if the event queue is full
{
if (ixEthDBPeek(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS) != IX_ETH_DB_NO_SUCH_ADDR)
{
- return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, FALSE);
+ return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, false);
}
else
{
/* enable port, VLAN and Firewall feature bits to initialize QoS/VLAN/Firewall configuration */
portInfo->featureStatus |= IX_ETH_DB_VLAN_QOS;
portInfo->featureStatus |= IX_ETH_DB_FIREWALL;
- portInfo->enabled = TRUE;
+ portInfo->enabled = true;
#define CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
ixEthDBPortVlanMembershipRangeRemove(portIndex, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID);
/* clear TTI table - no VLAN tagged frames will be transmitted */
- ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, FALSE);
+ ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, false);
/* set membership on 0, otherwise no Tx or Rx is working */
ixEthDBPortVlanMembershipAdd(portIndex, 0);
#endif
/* by default we turn off invalid source MAC address filtering */
- ixEthDBFirewallInvalidAddressFilterEnable(portIndex, FALSE);
+ ixEthDBFirewallInvalidAddressFilterEnable(portIndex, false);
/* disable port, VLAN, Firewall feature bits */
portInfo->featureStatus &= ~IX_ETH_DB_VLAN_QOS;
portInfo->featureStatus &= ~IX_ETH_DB_FIREWALL;
- portInfo->enabled = FALSE;
+ portInfo->enabled = false;
/* enable filtering by default if present */
if ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0)
*
* @param portID ID of the port
* @param feature feature to enable or disable
- * @param enabled TRUE to enable the selected feature or FALSE to disable it
+ * @param enabled true to enable the selected feature or false to disable it
*
* Note that this function is documented in the main component
* header file, IxEthDB.h.
}
/* force port enabled */
- portInfo->enabled = TRUE;
+ portInfo->enabled = true;
if (enable)
{
/* enable TPID port extraction */
if (status == IX_ETH_DB_SUCCESS)
{
- status = ixEthDBVlanPortExtractionEnable(portID, TRUE);
+ status = ixEthDBVlanPortExtractionEnable(portID, true);
}
}
else if (feature == IX_ETH_DB_FIREWALL)
if (status == IX_ETH_DB_SUCCESS)
{
- status = ixEthDBFirewallInvalidAddressFilterEnable(portID, FALSE);
+ status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false);
}
}
}
if (status == IX_ETH_DB_SUCCESS)
{
- status = ixEthDBFirewallInvalidAddressFilterEnable(portID, FALSE);
+ status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false);
}
if (status == IX_ETH_DB_SUCCESS)
/* disable TPID port extraction */
if (status == IX_ETH_DB_SUCCESS)
{
- status = ixEthDBVlanPortExtractionEnable(portID, FALSE);
+ status = ixEthDBVlanPortExtractionEnable(portID, false);
}
}
#endif
*
* @param portID port ID
* @param present location to store a boolean value indicating
- * if the feature is present (TRUE) or not (FALSE)
+ * if the feature is present (true) or not (false)
* @param enabled location to store a booleam value indicating
- * if the feature is present (TRUE) or not (FALSE)
+ * if the feature is present (true) or not (false)
*
* Note that this function is documented in the main component
* header file, IxEthDB.h.
UINT32 mode = 0;
PortInfo *portInfo = &ixEthDBPortInfo[portID];
- mode = (portInfo->srcAddressFilterEnabled != FALSE) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST);
+ mode = (portInfo->srcAddressFilterEnabled != false) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST);
FILL_SETFIREWALLMODE_MSG(message,
IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID),
* @brief enables or disables the invalid source MAC address filter
*
* @param portID ID of the port
- * @param enable TRUE to enable invalid source MAC address filtering
- * or FALSE to disable it
+ * @param enable true to enable invalid source MAC address filtering
+ * or false to disable it
*
* The invalid source MAC address filter will discard, when enabled,
* frames whose source MAC address is a multicast or the broadcast MAC
* collisions, i.e. descriptors with different mac addresses and the same
* hash value, where this function is used to differentiate entries.
*
- * @retval TRUE if the entry matches the reference key (equal addresses)
- * @retval FALSE if the entry does not match the reference key
+ * @retval true if the entry matches the reference key (equal addresses)
+ * @retval false if the entry does not match the reference key
*
* @internal
*/
/* debug */
IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) checking node at offset %d...\n", eltEntryOffset / ELT_ENTRY_SIZE);
- if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != TRUE)
+ if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != true)
{
IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is empty\n");
}
*
* @param typeArray array indexed on record types, each
* element indicating whether the record type requires an
- * automatic update (TRUE) or not (FALSE)
+ * automatic update (true) or not (false)
*
* Automatic updates are done for registered record types
* upon adding, updating (that is, updating the record portID)
*
* It is assumed that the typeArray parameter is allocated large
* enough to hold all the user defined types. Also, the type
- * array should be initialized to FALSE as this function only
+ * array should be initialized to false as this function only
* caters for types which do require automatic updates.
*
* Note that this function should be called by the component
IX_ETH_DB_PUBLIC
UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray)
{
- typeArray[IX_ETH_DB_FILTERING_RECORD] = TRUE;
- typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = TRUE;
+ typeArray[IX_ETH_DB_FILTERING_RECORD] = true;
+ typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = true;
return 2;
}
{
UINT32 portIndex;
BOOL result;
- BOOL portsLeft = TRUE;
+ BOOL portsLeft = true;
while (portsLeft)
{
}
/* mark tree as valid */
- port->updateMethod.searchTreePendingWrite = TRUE;
+ port->updateMethod.searchTreePendingWrite = true;
}
else
{
- portsLeft = FALSE;
+ portsLeft = false;
IX_ETH_DB_UPDATE_TRACE("DB: (Update) No trees to create this round\n");
}
/* forget last used search tree */
port->updateMethod.searchTree = NULL;
- port->updateMethod.searchTreePendingWrite = FALSE;
+ port->updateMethod.searchTreePendingWrite = false;
/* dependending on the update type we do different things */
if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD)
}
else
{
- ixEthDBPortInfo[portID].agingEnabled = FALSE;
- ixEthDBPortInfo[portID].updateMethod.updateEnabled = FALSE;
- ixEthDBPortInfo[portID].updateMethod.userControlled = TRUE;
+ ixEthDBPortInfo[portID].agingEnabled = false;
+ ixEthDBPortInfo[portID].updateMethod.updateEnabled = false;
+ ixEthDBPortInfo[portID].updateMethod.userControlled = true;
ERROR_LOG("EthDB: (PortUpdate) disabling aging and updates on port %d (assumed dead)\n", portID);
IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map)
{
UINT32 portIndex;
- BOOL mapSelf = TRUE, mapNone = TRUE, firstPort = TRUE;
+ BOOL mapSelf = true, mapNone = true, firstPort = true;
/* dependency port maps */
printf("Dependency port map: ");
{
if (IS_PORT_INCLUDED(portIndex, map))
{
- mapNone = FALSE;
+ mapNone = false;
if (portIndex != portID)
{
- mapSelf = FALSE;
+ mapSelf = false;
}
printf("%s%d", firstPort ? "{" : ", ", portIndex);
- firstPort = FALSE;
+ firstPort = false;
}
}
if (mapNone)
{
- mapSelf = FALSE;
+ mapSelf = false;
}
printf("%s (%s)\n", firstPort ? "" : "}", mapSelf ? "self" : mapNone ? "none" : "group");
* @param untypedReference record to match against
* @param untypedEntry record to match
*
- * @return TRUE if the match is successful or FALSE otherwise
+ * @return true if the match is successful or false otherwise
*
* @internal
*/
MacDescriptor *reference = (MacDescriptor *) untypedReference;
/* check accepted record types */
- if ((entry->type & reference->type) == 0) return FALSE;
+ if ((entry->type & reference->type) == 0) return false;
return (ixEthDBAddressCompare((UINT8 *) entry->macAddress, (UINT8 *) reference->macAddress) == 0);
}
* @param untypedReference record to match against
* @param untypedEntry record to match
*
- * @return TRUE if the match is successful or FALSE otherwise
+ * @return true if the match is successful or false otherwise
*
* @internal
*/
MacDescriptor *reference = (MacDescriptor *) untypedReference;
/* check accepted record types */
- if ((entry->type & reference->type) == 0) return FALSE;
+ if ((entry->type & reference->type) == 0) return false;
return (IX_ETH_DB_GET_VLAN_ID(entry->recordData.filteringVlanData.ieee802_1qTag) ==
IX_ETH_DB_GET_VLAN_ID(reference->recordData.filteringVlanData.ieee802_1qTag)) &&
* @param untypedReference record to match against
* @param untypedEntry record to match
*
- * @return TRUE if the match is successful or FALSE otherwise
+ * @return true if the match is successful or false otherwise
*
* @internal
*/
MacDescriptor *reference = (MacDescriptor *) untypedReference;
/* check accepted record types */
- if ((entry->type & reference->type) == 0) return FALSE;
+ if ((entry->type & reference->type) == 0) return false;
return (entry->portID == reference->portID) &&
(ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0);
* array on invalid types. Calling it will display an
* error message, indicating an error in the component logic.
*
- * @return FALSE
+ * @return false
*
* @internal
*/
ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, "DB: (Search) The NullMatch function was called, wrong key type?\n", 0, 0, 0, 0, 0, 0);
- return FALSE;
+ return false;
}
/**
* @brief sets the STP blocking state of a port
*
* @param portID ID of the port
- * @param blocked TRUE to block the port or FALSE to unblock it
+ * @param blocked true to block the port or false to unblock it
*
* Note that this function is documented in the main component
* header file, IxEthDB.h.
while (value != 0)
{
- if (value == 1) return TRUE;
- else if ((value & 1) == 1) return FALSE;
+ if (value == 1) return true;
+ else if ((value & 1) == 1) return false;
value >>= 1;
}
- return FALSE;
+ return false;
#endif
}
*
* @param portID ID of the port
* @param vlanID VLAN ID to enable or disable Egress tagging on
- * @param enabled TRUE to enable and FALSE to disable tagging
+ * @param enabled true to enable and false to disable tagging
*
* Note that this function is documented in the main component
* header file, IxEthDB.h.
* @param portID ID of the port
* @param vlanID VLAN ID to retrieve the tagging status for
* @param enabled location to store the tagging status
- * (TRUE - tagging enabled, FALSE - tagging disabled)
+ * (true - tagging enabled, false - tagging disabled)
*
* Note that this function is documented in the main component
* header file, IxEthDB.h.
* @param portID ID of the port
* @param vlanIDMin start of VLAN range
* @param vlanIDMax end of VLAN range
- * @param enabled TRUE to enable or FALSE to disable VLAN tagging
+ * @param enabled true to enable or false to disable VLAN tagging
*
* Note that this function is documented in the main component
* header file, IxEthDB.h.
* from the VLAN TPID field
*
* @param portID ID of the port
- * @param enable TRUE to enable or FALSE to disable
+ * @param enable true to enable or false to disable
*
* Note that this function is documented in the main component
* header file, IxEthDB.h.
* Scan for PHYs on the MII bus. This function returns
* an array of booleans, one for each PHY address.
* If a PHY is found at a particular address, the
- * corresponding entry in the array is set to TRUE.
+ * corresponding entry in the array is set to true.
*
*/
i<IXP425_ETH_ACC_MII_MAX_ADDR;
i++)
{
- phyPresent[i] = FALSE;
+ phyPresent[i] = false;
}
/* iterate through the PHY addresses */
)
{
/* supported phy */
- phyPresent[i] = TRUE;
+ phyPresent[i] = true;
} /* end of if(ixEthMiiPhyId) */
else
{
"ixEthMiiPhyScan : unexpected Mii PHY ID %8.8x\n",
ixEthMiiPhyId[i], 2, 3, 4, 5, 6);
ixEthMiiPhyId[i] = IX_ETH_MII_UNKNOWN_PHY_ID;
- phyPresent[i] = TRUE;
+ phyPresent[i] = true;
}
}
}
return IX_FAIL;
}
- *linkUp = FALSE;
- *speed100 = FALSE;
- *fullDuplex = FALSE;
- *autoneg = FALSE;
+ *linkUp = false;
+ *speed100 = false;
+ *fullDuplex = false;
+ *autoneg = false;
if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) &&
(ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID))
if ((regval & IX_ETH_MII_SR_TX_FULL_DPX) != 0)
{
/* 100 Base X full dplx */
- *speed100 = TRUE;
- *fullDuplex = TRUE;
+ *speed100 = true;
+ *fullDuplex = true;
return IX_SUCCESS;
}
if ((regval & IX_ETH_MII_SR_TX_HALF_DPX) != 0)
{
/* 100 Base X half dplx */
- *speed100 = TRUE;
+ *speed100 = true;
return IX_SUCCESS;
}
if ((regval & IX_ETH_MII_SR_10T_FULL_DPX) != 0)
{
/* 10 mb full dplx */
- *fullDuplex = TRUE;
+ *fullDuplex = true;
return IX_SUCCESS;
}
if ((regval & IX_ETH_MII_SR_10T_HALF_DPX) != 0)
/* Boolean to mark the fact that the EXP_CONFIG address space was mapped */
-PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = FALSE;
+PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = false;
/* Pointer holding the virtual address of the Feature Control Register */
PRIVATE VUINT32 *ixFeatureCtrlRegister = NULL;
PRIVATE BOOL swConfiguration[IX_FEATURECTRL_SWCONFIG_MAX];
/* Flag to control swConfiguration[] is initialized once */
-PRIVATE BOOL swConfigurationFlag = FALSE ;
+PRIVATE BOOL swConfigurationFlag = false ;
/* Array containing component mask values */
#ifdef __ixp42X
/* If the EXP Configuration space has already been mapped then
* return */
- if (ixFeatureCtrlExpCfgRegionMapped == TRUE)
+ if (ixFeatureCtrlExpCfgRegionMapped == true)
{
return;
}
(VUINT32 *) (expCfgBaseAddress + IX_FEATURE_CTRL_REG_OFFSET);
/* Mark the fact that the EXP_CONFIG space has already been mapped */
- ixFeatureCtrlExpCfgRegionMapped = TRUE;
+ ixFeatureCtrlExpCfgRegionMapped = true;
}
/**
PRIVATE void ixFeatureCtrlSwConfigurationInit(void)
{
UINT32 i;
- if (FALSE == swConfigurationFlag)
+ if (false == swConfigurationFlag)
{
for (i=0; i<IX_FEATURECTRL_SWCONFIG_MAX ; i++)
{
/* By default, all software configuration are enabled */
- swConfiguration[i]= TRUE ;
+ swConfiguration[i]= true ;
}
/*Make sure this function only initializes swConfiguration[] once*/
- swConfigurationFlag = TRUE ;
+ swConfigurationFlag = true ;
}
}
extern IxFeatureCtrlProductId AsmixFeatureCtrlProductIdRead();
#ifndef IN_KERNEL
- mode = SetKMode(TRUE);
+ mode = SetKMode(true);
#endif
pdId = AsmixFeatureCtrlProductIdRead();
#ifndef IN_KERNEL
ixFeatureCtrlSwConfigurationInit();
/* Check and return software configuration */
- return ((swConfiguration[(UINT32)swConfigType] == TRUE) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED);
+ return ((swConfiguration[(UINT32)swConfigType] == true) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED);
}
/**
*/
static IxNpeDlNpeState ixNpeDlNpeState[IX_NPEDL_NPEID_MAX] =
{
- {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
- {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
- {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}
+ {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
+ {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}},
+ {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}
};
static IxNpeDlStats ixNpeDlStats;
/*
* Software guard to prevent NPE from being started multiple times.
*/
-static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={FALSE, FALSE, FALSE} ;
+static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={false, false, false} ;
/*
if (IX_SUCCESS == status)
{
ixNpeDlNpeState[npeId].imageId = *imageIdPtr;
- ixNpeDlNpeState[npeId].validImage = TRUE;
+ ixNpeDlNpeState[npeId].validImage = true;
ixNpeDlStats.successfulDownloads++;
status = ixNpeDlNpeExecutionStart (npeId);
(status == IX_NPEDL_CRITICAL_MICROCODE_ERR))
{
ixNpeDlNpeState[npeId].imageId = *imageIdPtr;
- ixNpeDlNpeState[npeId].validImage = FALSE;
+ ixNpeDlNpeState[npeId].validImage = false;
ixNpeDlStats.criticalFailDownloads++;
}
} /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */
if (IX_SUCCESS == status)
{
/* Indicate NPE has been stopped */
- ixNpeDlNpeStarted[npeId] = FALSE ;
+ ixNpeDlNpeStarted[npeId] = false ;
}
return status;
} /* end of if-else(IX_NPEDL_NPEID_NPEC) */
} /* end of if not IXP42x-A0 Silicon */
- if (TRUE == ixNpeDlNpeStarted[npeId])
+ if (true == ixNpeDlNpeStarted[npeId])
{
/* NPE has been started. */
return IX_SUCCESS ;
if (IX_SUCCESS == status)
{
/* Indicate NPE has started */
- ixNpeDlNpeStarted[npeId] = TRUE ;
+ ixNpeDlNpeStarted[npeId] = true ;
}
IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
if (IX_SUCCESS == status)
{
/* Indicate NPE has been stopped */
- ixNpeDlNpeStarted[npeId] = FALSE ;
+ ixNpeDlNpeStarted[npeId] = false ;
}
return status;
* currently loaded images. If a critical error occured
* during download, record that the NPE has an invalid image
*/
- status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, TRUE);
+ status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, true);
if (IX_SUCCESS == status)
{
- ixNpeDlNpeState[npeId].validImage = TRUE;
+ ixNpeDlNpeState[npeId].validImage = true;
ixNpeDlStats.successfulDownloads++;
status = ixNpeDlNpeExecutionStart (npeId);
else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) ||
(status == IX_NPEDL_CRITICAL_MICROCODE_ERR))
{
- ixNpeDlNpeState[npeId].validImage = FALSE;
+ ixNpeDlNpeState[npeId].validImage = false;
ixNpeDlStats.criticalFailDownloads++;
}
{
IxNpeDlImageMgrImageLibraryHeader *header =
(IxNpeDlImageMgrImageLibraryHeader *) microCodeImageLibrary;
- BOOL result = TRUE;
+ BOOL result = true;
if (!header || header->signature != IX_NPEDL_IMAGEMGR_SIGNATURE)
{
- result = FALSE;
+ result = false;
ixNpeDlImageMgrStats.invalidSignature++;
}
(imageIdA->major == imageIdB->major) &&
(imageIdA->minor == imageIdB->minor))
{
- return TRUE;
+ return true;
}
else
{
- return FALSE;
+ return false;
}
}
if ((imageIdA->npeId == imageIdB->npeId) &&
(imageIdA->functionalityId == imageIdB->functionalityId))
{
- return TRUE;
+ return true;
}
else
{
- return FALSE;
+ return false;
}
}
UINT32 imageCount = 0;
IX_STATUS status = IX_FAIL;
IxNpeDlImageMgrImageLibraryHeader *header;
- BOOL imageFound = FALSE;
+ BOOL imageFound = false;
IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
"Entering ixNpeDlImageMgrImageFind\n");
/* get the image size */
*imageSize = header->entry[imageCount].image.size;
status = IX_SUCCESS;
- imageFound = TRUE;
+ imageFound = true;
}
imageCount++;
}
static IxNpeDlNpeMgrStats ixNpeDlNpeMgrStats;
/* Set when NPE register memory has been mapped */
-static BOOL ixNpeDlMemInitialised = FALSE;
+static BOOL ixNpeDlMemInitialised = false;
/*
IX_OSAL_ASSERT(virtAddr);
ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = virtAddr;
- ixNpeDlMemInitialised = TRUE;
+ ixNpeDlMemInitialised = true;
}
}
ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = 0;
ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = 0;
- ixNpeDlMemInitialised = FALSE;
+ ixNpeDlMemInitialised = false;
return IX_SUCCESS;
}
{
/* for each physical register in the NPE reg file, write 0 : */
status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr,
- 0, TRUE);
+ 0, true);
if (status != IX_SUCCESS)
{
return status; /* abort reset */
{
regVal = ixNpeDlCtxtRegResetValues[ctxtReg];
status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum,
- ctxtReg, regVal, TRUE);
+ ctxtReg, regVal, true);
if (status != IX_SUCCESS)
{
return status; /* abort reset */
* static variables.
*/
-PRIVATE BOOL ixNpeMhInitialized = FALSE;
+PRIVATE BOOL ixNpeMhInitialized = false;
/*
* Extern function prototypes.
*/
ixNpeMhConfigInitialize (npeInterrupts);
- ixNpeMhInitialized = TRUE;
+ ixNpeMhInitialized = true;
IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
"ixNpeMhInitialize\n");
/* Uninitialize the Configuration module */
ixNpeMhConfigUninit ();
- ixNpeMhInitialized = FALSE;
+ ixNpeMhInitialized = false;
IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting "
"ixNpeMhUnload\n");
0,
0,
NULL,
- FALSE
+ false
},
{
0,
0,
0,
NULL,
- FALSE
+ false
},
{
0,
0,
0,
NULL,
- FALSE
+ false
}
};
IxNpeMhNpeId npeId,
UINT32 maxSendRetries)
{
- BOOL isFull = FALSE;
+ BOOL isFull = false;
UINT32 numRetries = 0;
/* check the NPE's inFIFO */
static int drv_mutex_trylock(IxOsalMutex *mutex)
{
- int result = TRUE;
+ int result = true;
if (*mutex == 1)
- result = FALSE;
+ result = false;
return result;
}
/*
* This flag indicates to the dispatcher that the priority table needs to be rebuilt.
*/
-static BOOL rebuildTable = FALSE;
+static BOOL rebuildTable = false;
/* Dispatcher statistics */
static IxQMgrDispatcherStats dispatcherStats;
int i;
IxFeatureCtrlProductId productId = 0;
IxFeatureCtrlDeviceId deviceId = 0;
- BOOL stickyIntSilicon = TRUE;
+ BOOL stickyIntSilicon = true;
/* Set default priorities */
for (i=0; i< IX_QMGR_MAX_NUM_QUEUES; i++)
dispatcherStats.queueStats[i].priorityChangeCnt = 0;
dispatcherStats.queueStats[i].intNoCallbackCnt = 0;
dispatcherStats.queueStats[i].intLostCallbackCnt = 0;
- dispatcherStats.queueStats[i].notificationEnabled = FALSE;
+ dispatcherStats.queueStats[i].notificationEnabled = false;
dispatcherStats.queueStats[i].srcSel = 0;
}
(IX_FEATURE_CTRL_SILICON_TYPE_A0 ==
(IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId)))
{
- stickyIntSilicon = FALSE;
+ stickyIntSilicon = false;
}
/*
/* Change priority */
dispatchQInfo[qId].priority = priority;
/* Set flag */
- rebuildTable = TRUE;
+ rebuildTable = true;
ixOsalIrqUnlock(ixQMgrLockKey);
#endif
#ifndef NDEBUG
- dispatcherStats.queueStats[qId].notificationEnabled = TRUE;
+ dispatcherStats.queueStats[qId].notificationEnabled = true;
dispatcherStats.queueStats[qId].srcSel = srcSel;
#endif
* so need critical section
*/
#ifndef NDEBUG
- dispatcherStats.queueStats[qId].notificationEnabled = FALSE;
+ dispatcherStats.queueStats[qId].notificationEnabled = false;
#endif
ixQMgrLockKey = ixOsalIrqLock();
qIndex += IX_QMGR_MIN_QUEUPP_QID;
}
- if (statusChangeFlag == FALSE)
+ if (statusChangeFlag == false)
{
/* check if the interrupt register contains
* only 1 bit set (happy day scenario)
* For example:
* intRegVal = 0x0010
* currDispatchQInfo->intRegCheckMask = 0x0010
- * intRegVal == currDispatchQInfo->intRegCheckMask is TRUE.
+ * intRegVal == currDispatchQInfo->intRegCheckMask is true.
*/
currDispatchQInfo = &dispatchQInfo[qIndex];
if (intRegVal == currDispatchQInfo->intRegCheckMask)
* For example:
* intRegVal = 0x0010
* currDispatchQInfo->intRegCheckMask = 0x0010
- * intRegVal == currDispatchQInfo->intRegCheckMask is TRUE.
+ * intRegVal == currDispatchQInfo->intRegCheckMask is true.
*/
currDispatchQInfo = &dispatchQInfo[qIndex];
if (intRegVal == currDispatchQInfo->intRegCheckMask)
int uppQuePriorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX;
/* Reset the rebuild flag */
- rebuildTable = FALSE;
+ rebuildTable = false;
/* initialize the mak used to identify the queues in the first half
* of the priority table
* Update statistics
*/
dispatcherStats.queueStats[i].enableCount++;
- dispatcherStats.queueStats[i].notificationEnabled = TRUE;
+ dispatcherStats.queueStats[i].notificationEnabled = true;
#endif
}
}
* Set to true if initialized
* N.B. global so integration/unit tests can reinitialize
*/
-BOOL qMgrIsInitialized = FALSE;
+BOOL qMgrIsInitialized = false;
/*
* Function definitions.
ixQMgrQAccessInit ();
/* Initialization complete */
- qMgrIsInitialized = TRUE;
+ qMgrIsInitialized = true;
return IX_SUCCESS;
}
ixQMgrQCfgUninit ();
/* Uninitialization complete */
- qMgrIsInitialized = FALSE;
+ qMgrIsInitialized = false;
return IX_SUCCESS;
}
char qName[IX_QMGR_MAX_QNAME_LEN+1]; /* Textual description of a queue*/
IxQMgrQSizeInWords qSizeInWords; /* The number of words in the queue */
IxQMgrQEntrySizeInWords qEntrySizeInWords; /* Number of words per queue entry*/
- BOOL isConfigured; /* This flag is TRUE if the queue has
+ BOOL isConfigured; /* This flag is true if the queue has
* been configured
*/
} IxQMgrCfgQ;
/* 4 words of zeroed memory for inline access */
static UINT32 zeroedPlaceHolder[4] = { 0, 0, 0, 0 };
-static BOOL cfgInitialized = FALSE;
+static BOOL cfgInitialized = false;
static IxOsalMutex ixQMgrQCfgMutex;
strcpy (cfgQueueInfo[loopIndex].qName, "");
cfgQueueInfo[loopIndex].qSizeInWords = 0;
cfgQueueInfo[loopIndex].qEntrySizeInWords = 0;
- cfgQueueInfo[loopIndex].isConfigured = FALSE;
+ cfgQueueInfo[loopIndex].isConfigured = false;
/* Statistics */
- stats.qStats[loopIndex].isConfigured = FALSE;
+ stats.qStats[loopIndex].isConfigured = false;
stats.qStats[loopIndex].qName = cfgQueueInfo[loopIndex].qName;
}
ixOsalMutexInit(&ixQMgrQCfgMutex);
- cfgInitialized = TRUE;
+ cfgInitialized = true;
}
void
ixQMgrQCfgUninit (void)
{
- cfgInitialized = FALSE;
+ cfgInitialized = false;
/* Uninitialise the AqmIf component */
ixQMgrAqmIfUninit ();
IX_QMGR_QUE_BUFFER_SPACE_SIZE);
/* The queue is now configured */
- cfgQueueInfo[qId].isConfigured = TRUE;
+ cfgQueueInfo[qId].isConfigured = true;
ixOsalMutexUnlock(&ixQMgrQCfgMutex);
#ifndef NDEBUG
/* Update statistics */
- stats.qStats[qId].isConfigured = TRUE;
+ stats.qStats[qId].isConfigured = true;
stats.qStats[qId].qName = cfgQueueInfo[qId].qName;
#endif
return IX_SUCCESS;
{
if (!IX_QMGR_QID_IS_VALID(qId))
{
- return FALSE;
+ return false;
}
return cfgQueueInfo[qId].isConfigured;
case IX_QMGR_Q_WM_LEVEL64:
break;
default:
- return FALSE;
+ return false;
}
/* Check watermark is not bigger than the qSizeInEntries */
if ((unsigned)level > qSizeInEntries)
{
- return FALSE;
+ return false;
}
- return TRUE;
+ return true;
}
PRIVATE BOOL
case IX_QMGR_Q_SIZE32:
case IX_QMGR_Q_SIZE64:
case IX_QMGR_Q_SIZE128:
- status = TRUE;
+ status = true;
break;
default:
- status = FALSE;
+ status = false;
break;
}
case IX_QMGR_Q_ENTRY_SIZE1:
case IX_QMGR_Q_ENTRY_SIZE2:
case IX_QMGR_Q_ENTRY_SIZE4:
- status = TRUE;
+ status = true;
break;
default:
- status = FALSE;
+ status = false;
break;
}
* @brief disable a PHY logical port
*
* This function indicates if the port disable for a port has completed. This
-* function will return TRUE if the port has never been enabled.
+* function will return true if the port has never been enabled.
*
* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1]
*
-* @return @li TRUE disable is complete
-* @return @li FALSE disable failed, wrong parameter .
+* @return @li true disable is complete
+* @return @li false disable failed, wrong parameter .
*
* @note - This function needs internal locks and should not be called
* from an interrupt context
#define IX_ETH_ACC_PUBLIC
-#define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? TRUE : FALSE )
+#define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? true : false )
#define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized)
extern BOOL ixEthAccServiceInit;
-#define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == TRUE )
+#define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == true )
/*
* Maximum number of frames to consume from the Rx Frame Q.
IX_ETH_DB_INTEGER_PROPERTY = 0x1, /**< 4 byte unsigned integer type */
IX_ETH_DB_STRING_PROPERTY = 0x2, /**< NULL-terminated string type of maximum 255 characters (including the terminator) */
IX_ETH_DB_MAC_ADDR_PROPERTY = 0x3, /**< 6 byte MAC address type */
- IX_ETH_DB_BOOL_PROPERTY = 0x4 /**< 4 byte boolean type; can contain only TRUE and FALSE values */
+ IX_ETH_DB_BOOL_PROPERTY = 0x4 /**< 4 byte boolean type; can contain only true and false values */
} IxEthDBPropertyType;
/* list of supported properties for the IX_ETH_DB_VLAN_QOS feature */
*
* @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on
* @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be matched against outgoing frames
- * @param enabled BOOL [in] - TRUE to enable Egress VLAN tagging on the port and given VLAN, and
- * FALSE to disable Egress VLAN tagging
+ * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN, and
+ * false to disable Egress VLAN tagging
*
* @retval IX_ETH_DB_SUCCESS operation completed successfully
* @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
* @param portID [in] - ID of the port to extract the Egress VLAN ID tagging status from
* @param vlanID VLAN [in] - ID whose tagging status is to be extracted
* @param enabled [in] - user-specifed location where the status is copied to; following
- * the successfull execution of this function the value will be TRUE if Egress VLAN
- * tagging is enabled for the given port and VLAN ID, and FALSE otherwise
+ * the successfull execution of this function the value will be true if Egress VLAN
+ * tagging is enabled for the given port and VLAN ID, and false otherwise
*
* - Reentrant - no
* - ISR Callable - no
* @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on
* @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN range to be matched against outgoing frames
* @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN range to be matched against outgoing frames
- * @param enabled BOOL [in] - TRUE to enable Egress VLAN tagging on the port and given VLAN range,
- * and FALSE to disable Egress VLAN tagging
+ * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN range,
+ * and false to disable Egress VLAN tagging
*
* @retval IX_ETH_DB_SUCCESS operation completed successfully
* @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
* This feature is disabled by default.
*
* @param portID ID of the port to configure port ID extraction on
- * @param enable TRUE to enable port ID extraction and FALSE to disable it
+ * @param enable true to enable port ID extraction and false to disable it
*
* @retval IX_ETH_DB_SUCCESS operation completed successfully
* @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
*
* @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the features on (use IX_ETH_DB_ALL_PORTS for all the ports)
* @param feature @ref IxEthDBFeature [in] - feature or feature set to enable or disable
- * @param enabled BOOL [in] - TRUE to enable the feature and FALSE to disable it
+ * @param enabled BOOL [in] - true to enable the feature and false to disable it
*
* @note Certain features, from a functional point of view, cannot be disabled as such at NPE level;
* when such features are set to <i>disabled</i> using the EthDB API they will be configured in such
*
* This function returns the availability and status for a feature set.
* Note that if more than one feature is selected (e.g. IX_ETH_DB_LEARNING | IX_ETH_DB_FILTERING)
- * the "present" and "enabled" return values will be set to TRUE only if all the features in the
+ * the "present" and "enabled" return values will be set to true only if all the features in the
* feature set are present and enabled (not only some).
*
* @param portID @ref IxEthDBPortId [in] - ID of the port
* - IX_ETH_DB_INTEGER_PROPERTY - 4 bytes are copied from the source location
* - IX_ETH_DB_STRING_PROPERTY - the source string will be copied up to the NULL '\0' string terminator, maximum of 255 characters
* - IX_ETH_DB_MAC_ADDR_PROPERTY - 6 bytes are copied from the source location
- * - IX_ETH_DB_BOOL_PROPERTY - 4 bytes are copied from the source location; the only allowed values are TRUE (1L) and false (0L)
+ * - IX_ETH_DB_BOOL_PROPERTY - 4 bytes are copied from the source location; the only allowed values are true (1L) and false (0L)
*
* @see ixEthDBFeaturePropertySet
*
* @brief Sets the STP blocked/unblocked state for a port
*
* @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param blocked BOOL [in] - TRUE to set the port as STP blocked, FALSE to set it as unblocked
+ * @param blocked BOOL [in] - true to set the port as STP blocked, false to set it as unblocked
*
* @retval IX_ETH_DB_SUCCESS operation completed successfully
* @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
* @brief Retrieves the STP blocked/unblocked state for a port
*
* @param portID @ref IxEthDBPortId [in] - ID of the port
- * @param blocked BOOL * [in] - set to TRUE if the port is STP blocked, FALSE otherwise
+ * @param blocked BOOL * [in] - set to true if the port is STP blocked, false otherwise
*
* @retval IX_ETH_DB_SUCCESS operation completed successfully
* @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
* NPE image.
*
* @param portID ID of the port
- * @param enable TRUE to enable invalid MAC address filtering and FALSE to disable it
+ * @param enable true to enable invalid MAC address filtering and false to disable it
*
* @retval IX_ETH_DB_SUCCESS operation completed successfully
* @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier
#define TREE_POOL_SIZE (4000) /**< number of MacTreeNode objects; each entry has 16 bytes */
/* retry policies */
-#define BUSY_RETRY_ENABLED (TRUE) /**< if set to TRUE the API will retry automatically calls returning BUSY */
-#define FOREVER_RETRY (TRUE) /**< if set to TRUE the API will retry forever BUSY calls */
-#define MAX_RETRIES (400) /**< upper retry limit - used only when FOREVER_RETRY is FALSE */
+#define BUSY_RETRY_ENABLED (true) /**< if set to true the API will retry automatically calls returning BUSY */
+#define FOREVER_RETRY (true) /**< if set to true the API will retry forever BUSY calls */
+#define MAX_RETRIES (400) /**< upper retry limit - used only when FOREVER_RETRY is false */
#define BUSY_RETRY_YIELD (5) /**< ticks to yield for every failed retry */
/* event management */
#define EVENT_PROCESSING_LIMIT (100) /**< batch processing control size (how many events are extracted from the queue at once) */
/* MAC descriptors */
-#define STATIC_ENTRY (TRUE)
-#define DYNAMIC_ENTRY (FALSE)
+#define STATIC_ENTRY (true)
+#define DYNAMIC_ENTRY (false)
/* age reset on next maintenance - incrementing by 1 will reset to 0 */
#define AGE_RESET (0xFFFFFFFF)
/* gives an empty dependency map */
#define SET_EMPTY_DEPENDENCY_MAP(map) { int i = 0; for (; i < 32 ; i++) map[i] = 0; }
-#define IS_EMPTY_DEPENDENCY_MAP(result, map) { int i = 0 ; result = TRUE; for (; i < 32 ; i++) if (map[i] != 0) { result = FALSE; break; }}
+#define IS_EMPTY_DEPENDENCY_MAP(result, map) { int i = 0 ; result = true; for (; i < 32 ; i++) if (map[i] != 0) { result = false; break; }}
/**
* gives a map consisting only of 'portID'
#define EXCLUDE_PORT_FROM_MAP(map, portID) { map[portID >> 3] &= ~(1 << (portID & 0x7); }
/**
- * returns TRUE if map1 is a subset of map2 and FALSE otherwise
+ * returns true if map1 is a subset of map2 and false otherwise
*/
-#define IS_MAP_SUBSET(result, map1, map2) { int i = 0; result = TRUE; for (; i < 32 ; i++) if ((map1[i] | map2[i]) != map2[i]) result = FALSE; }
+#define IS_MAP_SUBSET(result, map1, map2) { int i = 0; result = true; for (; i < 32 ; i++) if ((map1[i] | map2[i]) != map2[i]) result = false; }
/**
- * returns TRUE is portID is part of map and FALSE otherwise
+ * returns true is portID is part of map and false otherwise
*/
#define IS_PORT_INCLUDED(portID, map) ((map[portID >> 3] & (1 << (portID & 0x7))) != 0)
#define DIFF_MAPS(map, map1, map2) { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] ^ (map1[i] & map2[i]); }
/**
- * returns TRUE if the maps collide (have at least one port in common) and FALSE otherwise
+ * returns true if the maps collide (have at least one port in common) and false otherwise
*/
-#define MAPS_COLLIDE(result, map1, map2) { int i = 0; result = FALSE; for (; i < 32 ; i++) if ((map1[i] & map2[i]) != 0) result = TRUE; }
+#define MAPS_COLLIDE(result, map1, map2) { int i = 0; result = false; for (; i < 32 ; i++) if ((map1[i] & map2[i]) != 0) result = true; }
/* size (number of ports) of a dependency map */
#define GET_MAP_SIZE(map, size) { int i = 0, b = 0; size = 0; for (; i < 32 ; i++) { char y = map[i]; for (; b < 8 && (y >>= 1); b++) size += (y & 1); }}
struct
{
UINT32 age;
- BOOL staticEntry; /**< TRUE if this address is static (doesn't age) */
+ BOOL staticEntry; /**< true if this address is static (doesn't age) */
} filteringData;
struct
typedef struct
{
- BOOL updateEnabled; /**< TRUE if updates are enabled for port */
- BOOL userControlled; /**< TRUE if the user has manually used ixEthDBPortUpdateEnableSet */
- BOOL treeInitialized; /**< TRUE if the NPE has received an initial tree */
+ BOOL updateEnabled; /**< true if updates are enabled for port */
+ BOOL userControlled; /**< true if the user has manually used ixEthDBPortUpdateEnableSet */
+ BOOL treeInitialized; /**< true if the NPE has received an initial tree */
IxEthDBPortUpdateHandler updateHandler; /**< port update handler routine */
void *npeUpdateZone; /**< port update memory zone */
void *npeGwUpdateZone; /**< port update memory zone for gateways */
void *vlanUpdateZone; /**< port update memory zone for VLAN tables */
MacTreeNode *searchTree; /**< internal search tree, in MacTreeNode representation */
- BOOL searchTreePendingWrite; /**< TRUE if searchTree holds a tree pending write to the port */
+ BOOL searchTreePendingWrite; /**< true if searchTree holds a tree pending write to the port */
} PortUpdateMethod;
typedef struct
{
IxEthDBPortId portID; /**< port ID */
- BOOL enabled; /**< TRUE if the port is enabled */
- BOOL agingEnabled; /**< TRUE if aging on this port is enabled */
+ BOOL enabled; /**< true if the port is enabled */
+ BOOL agingEnabled; /**< true if aging on this port is enabled */
BOOL initialized;
IxEthDBPortMap dependencyPortMap; /**< dependency port map for this port */
PortUpdateMethod updateMethod; /**< update method structure */
- BOOL macAddressUploaded; /**< TRUE if the MAC address was uploaded into the port */
+ BOOL macAddressUploaded; /**< true if the MAC address was uploaded into the port */
UINT32 maxRxFrameSize; /**< maximum Rx frame size for this port */
UINT32 maxTxFrameSize; /**< maximum Rx frame size for this port */
*
* @brief Scan the MDIO bus for PHYs
* This function scans PHY addresses 0 through 31, and sets phyPresent[n] to
- * TRUE if a phy is discovered at address n.
+ * true if a phy is discovered at address n.
*
* - Reentrant - no
* - ISR Callable - no
* @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
*
* @param phyAddr UINT32 [in]
- * @param speed100 BOOL [in] - set to TRUE for 100Mbit/s operation, FALSE for 10Mbit/s
- * @param fullDuplex BOOL [in] - set to TRUE for Full Duplex, FALSE for Half Duplex
- * @param autonegotiate BOOL [in] - set to TRUE to enable autonegotiation
+ * @param speed100 BOOL [in] - set to true for 100Mbit/s operation, false for 10Mbit/s
+ * @param fullDuplex BOOL [in] - set to true for Full Duplex, false for Half Duplex
+ * @param autonegotiate BOOL [in] - set to true to enable autonegotiation
*
* @return IX_STATUS
* - IX_SUCCESS
* @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock.
*
* @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31)
- * @param linkUp BOOL [out] - set to TRUE if the link is up
- * @param speed100 BOOL [out] - set to TRUE indicates 100Mbit/s, FALSE indicates 10Mbit/s
- * @param fullDuplex BOOL [out] - set to TRUE indicates Full Duplex, FALSE indicates Half Duplex
- * @param autoneg BOOL [out] - set to TRUE indicates autonegotiation is enabled, FALSE indicates autonegotiation is disabled
+ * @param linkUp BOOL [out] - set to true if the link is up
+ * @param speed100 BOOL [out] - set to true indicates 100Mbit/s, false indicates 10Mbit/s
+ * @param fullDuplex BOOL [out] - set to true indicates Full Duplex, false indicates Half Duplex
+ * @param autoneg BOOL [out] - set to true indicates autonegotiation is enabled, false indicates autonegotiation is disabled
*
* @return IX_STATUS
* - IX_SUCCESS
* @brief This function enable/disable the specified software configuration.
*
* Usage Example:<br>
- * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, TRUE) is used
+ * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, true) is used
* to enable Ethernet Learning Feature <br>
- * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, FALSE) is used
+ * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false) is used
* to disable Ethernet Learning Feature <br>
*
* @param swConfigType IxFeatureCtrlSwConfig [in] - the type of a software configuration
* defined in IxFeatureCtrlSwConfig enumeration.
- * @param enabled BOOL [in] - To enable(TRUE) / disable (FALSE) the specified software
+ * @param enabled BOOL [in] - To enable(true) / disable (false) the specified software
* configuration.
*
* @return none
*/
typedef struct
{
- BOOL hdlc56kMode; /**< 56kbps(TRUE)/64kbps(FALSE) HDLC */
+ BOOL hdlc56kMode; /**< 56kbps(true)/64kbps(false) HDLC */
IxHssAcc56kEndianness hdlc56kEndian; /**< 56kbps data endianness
- - ignored if hdlc56kMode is FALSE*/
- BOOL hdlc56kUnusedBitPolarity0; /**< The polarity '0'(TRUE)/'1'(FALSE) of the unused
+ - ignored if hdlc56kMode is false*/
+ BOOL hdlc56kUnusedBitPolarity0; /**< The polarity '0'(true)/'1'(false) of the unused
bit while in 56kbps mode
- - ignored if hdlc56kMode is FALSE*/
+ - ignored if hdlc56kMode is false*/
} IxHssAccHdlcMode;
/**
* to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3
*
* @return
- * - TRUE The state of this HSS/HDLC port combination is disconnected,
+ * - true The state of this HSS/HDLC port combination is disconnected,
* so if a disconnect was called, it is now completed.
- * - FALSE The state of this HSS/HDLC port combination is connected,
+ * - false The state of this HSS/HDLC port combination is connected,
* so if a disconnect was called, it is not yet completed.
*/
PUBLIC BOOL
* identical ports (0-1).
* @param *dataRecvd BOOL [out] - This BOOL indicates to the client whether
* or not the access component has read any data for the client. If
- * FALSE, the other output parameters will not have been written to.
+ * false, the other output parameters will not have been written to.
* @param *rxOffset unsigned [out] - An offset to indicate to the client
* where within the receive buffers the NPE has just written the received
* data to.
* @param imageIdPtr @ref IxNpeDlImageId* [in] - Pointer to Id of the microcode
* image to download.
* @param verify BOOL [in] - ON/OFF option to verify the download. If ON
- * (verify == TRUE), the Downloader will read back
+ * (verify == true), the Downloader will read back
* each word written to the NPE registers to
* ensure the download operation was successful.
*
* @param UINT32 [in] npeBaseAddress - Base Address of NPE
* @param UINT32 [in] insMemAddress - NPE instruction memory address to write
* @param UINT32 [in] insMemData - data to write to instruction memory
- * @param BOOL [in] verify - if TRUE, verify the memory location is
+ * @param BOOL [in] verify - if true, verify the memory location is
* written successfully.
*
* This function is used to write a single word of data to a location in NPE
* @post
*
* @return
- * - IX_FAIL if verify is TRUE and the memory location was not written
+ * - IX_FAIL if verify is true and the memory location was not written
* successfully
* - IX_SUCCESS otherwise
*/
* @param UINT32 [in] npeBaseAddress - Base Address of NPE
* @param UINT32 [in] dataMemAddress - NPE data memory address to write
* @param UINT32 [in] dataMemData - data to write to NPE data memory
- * @param BOOL [in] verify - if TRUE, verify the memory location is
+ * @param BOOL [in] verify - if true, verify the memory location is
* written successfully.
*
* This function is used to write a single word of data to a location in NPE
* @post
*
* @return
- * - IX_FAIL if verify is TRUE and the memory location was not written
+ * - IX_FAIL if verify is true and the memory location was not written
* successfully
* - IX_SUCCESS otherwise
*/
* @param UINT32 [in] npeBaseAddress - Base Address of NPE
* @param UINT32 [in] regAddr - number of the physical register (0-31)*
* @param UINT32 [in] regValue - value to write to the physical register
- * @param BOOL [in] verify - if TRUE, verify the register is written
+ * @param BOOL [in] verify - if true, verify the register is written
* successfully.
*
* This function writes a physical register in the NPE data register file.
* a sequence of calls to this function
*
* @return
- * - IX_FAIL if verify is TRUE and the Context Register was not written
+ * - IX_FAIL if verify is true and the Context Register was not written
* successfully
* - IX_SUCCESS if Context Register was written successfully
* - IX_NPEDL_CRITICAL_NPE_ERR if Context Register was not written
* @param IxNpeDlCtxtRegNum [in] ctxtReg - which Context Store reg to write
* @param UINT32 [in] ctxtRegVal - value to write to the Context Store
* register
- * @param BOOL [in] verify - if TRUE, verify the register is
+ * @param BOOL [in] verify - if true, verify the register is
* written successfully.
*
* This function writes the contents of a Context Store register in the NPE
* a sequence of calls to this function
*
* @return
- * - IX_FAIL if verify is TRUE and the Context Register was not written
+ * - IX_FAIL if verify is true and the Context Register was not written
* successfully
* - IX_SUCCESS if Context Register was written successfully
* - IX_NPEDL_CRITICAL_NPE_ERR if Context Register was not written
* @param IxNpeDlNpeId [in] npeId - Id of target NPE
* @param UINT32* [in] imageCodePtr - pointer to image code in image to be
* downloaded
- * @param BOOL [in] verify - if TRUE, verify each word written to
+ * @param BOOL [in] verify - if true, verify each word written to
* NPE memory.
*
* This function loads a image containing blocks of microcode onto a
UINT32 inFifoRegister; /**< inFIFO register virutal address */
UINT32 outFifoRegister; /**< outFIFO register virtual address */
IxNpeMhConfigIsr isr; /**< isr routine for handling interrupt */
- BOOL oldInterruptState; /**< old interrupt state (TRUE => enabled) */
+ BOOL oldInterruptState; /**< old interrupt state (true => enabled) */
} IxNpeMhConfigNpeInfo;
* @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
* be enabled.
*
- * @return Returns the previous state of the interrupt (TRUE => enabled).
+ * @return Returns the previous state of the interrupt (true => enabled).
*/
BOOL ixNpeMhConfigNpeInterruptEnable (
* @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will
* be disabled.
*
- * @return Returns the previous state of the interrupt (TRUE => enabled).
+ * @return Returns the previous state of the interrupt (true => enabled).
*/
BOOL ixNpeMhConfigNpeInterruptDisable (
*
* @param IxNpeMhNpeId npeId (in) - the NPE ID to validate.
*
- * @return True if the NPE ID is valid, otherwise False.
+ * @return true if the NPE ID is valid, otherwise false.
*/
BOOL ixNpeMhConfigNpeIdIsValid (
* @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
* will be checked.
*
- * @return True if the inFIFO is empty, otherwise False.
+ * @return true if the inFIFO is empty, otherwise false.
*/
IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsEmpty (
* @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO
* will be checked.
*
- * @return True if the inFIFO is full, otherwise False.
+ * @return true if the inFIFO is full, otherwise false.
*/
IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsFull (
* @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
* will be checked.
*
- * @return True if the outFIFO is empty, otherwise False.
+ * @return true if the outFIFO is empty, otherwise false.
*/
IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsEmpty (
* @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO
* will be checked.
*
- * @return True if the outFIFO is full, otherwise False.
+ * @return true if the outFIFO is full, otherwise false.
*/
IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsFull (
* @li Reentrant: yes
* @li IRQ safe: yes
*
- * @return - TRUE if the structures are equal
- * - FALSE otherwise
+ * @return - true if the structures are equal
+ * - false otherwise
* Note: This function is OS-independant
*/
#define IX_OSAL_TIME_EQ(tvA, tvB) \
* @li Reentrant: yes
* @li IRQ safe: yes
*
- * @return - TRUE if tvA < tvB
- * - FALSE otherwise
+ * @return - true if tvA < tvB
+ * - false otherwise
* Note: This function is OS-independent. Implemented by core.
*/
#define IX_OSAL_TIME_LT(tvA,tvB) \
* @li Reentrant: yes
* @li IRQ safe: yes
*
- * @return - TRUE if tvA > tvB
- * - FALSE otherwise
+ * @return - true if tvA > tvB
+ * - false otherwise
* Note: This function is OS-independent.
*/
#define IX_OSAL_TIME_GT(tvA, tvB) \
*/
#define IX_OSAL_BILLION (1000000000)
-#ifndef TRUE
-#define TRUE 1L
-#endif
-
-#if TRUE != 1
-#error TRUE is not defined to 1
-#endif
-
-#ifndef FALSE
-#define FALSE 0L
-#endif
-
-#if FALSE != 0
-#error FALSE is not defined to 0
-#endif
-
#ifndef NULL
#define NULL 0L
#endif
* Check if Xcycle measuring task is running.
*
* @return
- * - TRUE - Xcycle is running
- * - FALSE - Xcycle is not running
+ * - true - Xcycle is running
+ * - false - Xcycle is not running
*
* @li Reentrant : no
* @li ISR Callable : no
(newQStatusWords[statusWordOffset] & mask)) &&
((newQStatusWords[statusWordOffset] & mask) == checkValue))
{
- return TRUE;
+ return true;
}
- return FALSE;
+ return false;
}
/*
/*
* This inline function will read the status bit of a queue
- * specified by qId. If reset is TRUE the bit is cleared.
+ * specified by qId. If reset is true the bit is cleared.
*/
IX_QMGR_AQMIF_INLINE BOOL
ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId,
{
ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset));
}
- return TRUE;
+ return true;
}
/* Bit not set */
- return FALSE;
+ return false;
}
IX_QMGR_QUEUOSTAT0_OFFSET,
IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
IX_QMGR_UNDERFLOW_BIT_OFFSET,
- TRUE/*reset*/));
+ true/*reset*/));
}
else
{
/* Qs 32-63 have no underflow status */
- return FALSE;
+ return false;
}
}
IX_QMGR_QUEUOSTAT0_OFFSET,
IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
IX_QMGR_OVERFLOW_BIT_OFFSET,
- TRUE/*reset*/));
+ true/*reset*/));
}
else
{
/* Qs 32-63 have no overflow status */
- return FALSE;
+ return false;
}
}
IX_QMGR_QUEUPPSTAT0_OFFSET,
IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
0/*relativeBitOffset*/,
- FALSE/*!reset*/))
+ false/*!reset*/))
{
*status |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
}
IX_QMGR_QUEUPPSTAT1_OFFSET,
IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
0/*relativeBitOffset*/,
- FALSE/*!reset*/))
+ false/*!reset*/))
{
*status |= IX_QMGR_Q_STATUS_F_BIT_MASK;
}
*
* @brief Enables/disables the loopback mode
*
- * @param "BOOL [in] loopbackEnable" - True to enable and false to disable.
+ * @param "BOOL [in] loopbackEnable" - true to enable and false to disable.
*
* Global Data :
* - None.
* the Target Time in the IEEE 1588 hardware assist block. If the condition is
* true an event flag is set in the hardware.
*
- * @param ttmPollFlag [out] - TRUE if the target time reached/hit condition event set
- * FALSE if the target time reached/hit condition event is
+ * @param ttmPollFlag [out] - true if the target time reached/hit condition event set
+ * false if the target time reached/hit condition event is
not set
* @param targetTime [out] - Capture current targetTime into client provided buffer
*
* (Master or Slave)
*
* @param auxMode [in] - Auxiliary Snapshot Register (Slave or Master) to be checked
- * @param auxPollFlag [out] - TRUE if the time stamp captured in auxiliary
+ * @param auxPollFlag [out] - true if the time stamp captured in auxiliary
snapshot register
- * FALSE if the time stamp not captured in
+ * false if the time stamp not captured in
auxiliary snapshot register
* @param auxTime [out] - Copy the current Auxiliary Snapshot Register value into the
* client provided buffer
}
/* don't need this for U-Boot */
- ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, FALSE);
+ ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false);
if (ixEthAccInit() != IX_ETH_ACC_SUCCESS) {
printf("Error initialising Ethernet access driver!\n");
*/
if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
IX_FEATURE_CTRL_COMPONENT_ENABLED)
- npe_exists[IX_ETH_PORT_1] = TRUE;
+ npe_exists[IX_ETH_PORT_1] = true;
if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
IX_FEATURE_CTRL_COMPONENT_ENABLED)
- npe_exists[IX_ETH_PORT_2] = TRUE;
+ npe_exists[IX_ETH_PORT_2] = true;
break;
case IX_FEATURE_CTRL_SILICON_TYPE_A0:
/*
* If it is A0 Silicon, we enable both as both Eth Coprocessors
* are available.
*/
- npe_exists[IX_ETH_PORT_1] = TRUE;
- npe_exists[IX_ETH_PORT_2] = TRUE;
+ npe_exists[IX_ETH_PORT_1] = true;
+ npe_exists[IX_ETH_PORT_2] = true;
break;
}
} else if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X) {
if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
IX_FEATURE_CTRL_COMPONENT_ENABLED)
- npe_exists[IX_ETH_PORT_1] = TRUE;
+ npe_exists[IX_ETH_PORT_1] = true;
if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
IX_FEATURE_CTRL_COMPONENT_ENABLED)
- npe_exists[IX_ETH_PORT_2] = TRUE;
+ npe_exists[IX_ETH_PORT_2] = true;
}
npe_used[IX_ETH_PORT_1] = 1;
#define RTC_SR_BIT_AF 0x01 /* Bit 0 = Alarm Flag */
#define RTC_SR_BIT_OSF 0x80 /* Bit 7 - Osc Stop Flag */
-typedef unsigned char boolean_t;
-
-#ifndef TRUE
-#define TRUE ((boolean_t)(0==0))
-#endif
-#ifndef FALSE
-#define FALSE (!TRUE)
-#endif
-
const char RtcTodAddr[] = {
RTC_TOD_CNT_BYTE0_ADDR,
RTC_TOD_CNT_BYTE1_ADDR,
};
static uchar rtc_read (uchar reg);
-static void rtc_write (uchar reg, uchar val, boolean_t set);
+static void rtc_write(uchar reg, uchar val, bool set);
static void rtc_write_raw (uchar reg, uchar val);
/*
}
/* Start clock */
- rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, FALSE);
+ rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, false);
return 0;
}
struct rtc_time tmp;
/* clear status flags */
- rtc_write (RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), FALSE); /* clearing OSF and AF */
+ rtc_write(RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), false); /* clearing OSF and AF */
/* Initialise DS1374 oriented to MPC8349E-ADS */
rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC
|RTC_CTL_BIT_WACE
- |RTC_CTL_BIT_AIE), FALSE);/* start osc, disable WACE, clear AIE
+ |RTC_CTL_BIT_AIE), false);/* start osc, disable WACE, clear AIE
- set to 0 */
rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM
|RTC_CTL_BIT_WDSTR
|RTC_CTL_BIT_RS1
|RTC_CTL_BIT_RS2
- |RTC_CTL_BIT_BBSQW), TRUE);/* disable WD/ALM, WDSTR set to INT-pin,
+ |RTC_CTL_BIT_BBSQW), true);/* disable WD/ALM, WDSTR set to INT-pin,
set BBSQW and SQW to 32k
- set to 1 */
tmp.tm_year = 1970;
tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
- rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAC, TRUE);
- rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR,0xDE, TRUE);
- rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAD, TRUE);
+ rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAC, true);
+ rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR, 0xDE, true);
+ rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAD, true);
}
/*
return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
}
-static void rtc_write (uchar reg, uchar val, boolean_t set)
+static void rtc_write(uchar reg, uchar val, bool set)
{
- if (set == TRUE) {
+ if (set == true) {
val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg);
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
} else {
/*
* is_usbd_high_speed routine needs to be defined by
* specific gadget driver
- * It returns TRUE if device enumerates at High speed
- * Retuns FALSE otherwise
+ * It returns true if device enumerates at High speed
+ * Retuns false otherwise
*/
for (i = 0; i < NUM_ENDPOINTS; i++) {
if (((ep_descriptor_ptrs[i]->bmAttributes &
/*
* Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
- * below is True) or 0. In case the wait was for the bit(s) to set - write
+ * below is true) or 0. In case the wait was for the bit(s) to set - write
* those bits back, which would cause resetting them.
*
* Return the last read status value on success or -1 on failure.
#define __iomem
#define __deprecated
-typedef enum { false = 0, true = 1 } bool;
-
struct unused {};
typedef struct unused unused_t;
#define YES 1
#define NO 0
-#define TRUE 1
-#define FALSE 0
#define RECOVER 1
#define SCAN 0
static struct revoke_blk_list *revk_blk_list;
static struct revoke_blk_list *prev_node;
-static int first_node = TRUE;
+static int first_node = true;
int gindex;
int gd_index;
return;
memcpy(node->content, buffer, fs->blksz);
- if (first_node == TRUE) {
+ if (first_node == true) {
revk_blk_list = node;
prev_node = node;
- first_node = FALSE;
+ first_node = false;
} else {
prev_node->next = node;
prev_node = node;
revk_blk_list = NULL;
prev_node = NULL;
- first_node = TRUE;
+ first_node = true;
}
int check_blknr_for_revoke(long int blknr, int sequence_no)
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#define FALSE 0
-#define TRUE 1
-
-
#define ETHERNET_ADDRESS_SIZE 6
typedef unsigned char UCHAR;
((rc) & 0x1))
#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1)
-#ifndef FALSE
-#define FALSE 0
-#define TRUE (!FALSE)
-#endif
-
#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr))
#define MAX_OPERANDS 8
#define CONFIG_MAX_FPGA_DEVICES 5
#endif
-/* these probably belong somewhere else */
-#ifndef FALSE
-#define FALSE (0)
-#endif
-#ifndef TRUE
-#define TRUE (!FALSE)
-#endif
-
/* CONFIG_FPGA bit assignments */
#define CONFIG_SYS_FPGA_MAN(x) (x)
#define CONFIG_SYS_FPGA_DEV(x) ((x) << 8 )
/* includes */
#include "gt64260R.h"
+#include <stdbool.h>
extern unsigned int INTERNAL_REG_BASE_ADDR;
#define _1G 0x40000000
#define _2G 0x80000000
-#ifndef BOOL_WAS_DEFINED
-#define BOOL_WAS_DEFINED
-typedef enum _bool{false,true} bool;
-#endif
-
/* Little to Big endian conversion macros */
#ifdef LE /* Little Endian */
*/
#define BBT_AUTO_REFRESH 0x00000080
/*
- * Chip does not require ready check on read. True
+ * Chip does not require ready check on read. true
* for all large page devices, as they do not support
* autoincrement.
*/
#include <linux/posix_types.h>
#include <asm/types.h>
+#include <stdbool.h>
#ifndef __KERNEL_STRICT_NAMES
* driver setup() requests
* @ep_list: List of other endpoints supported by the device.
* @speed: Speed of current connection to USB host.
- * @is_dualspeed: True if the controller supports both high and full speed
+ * @is_dualspeed: true if the controller supports both high and full speed
* operation. If it does, the gadget driver must also support both.
- * @is_otg: True if the USB device port uses a Mini-AB jack, so that the
+ * @is_otg: true if the USB device port uses a Mini-AB jack, so that the
* gadget driver must provide a USB OTG descriptor.
- * @is_a_peripheral: False unless is_otg, the "A" end of a USB cable
+ * @is_a_peripheral: false unless is_otg, the "A" end of a USB cable
* is in the Mini-AB jack, and HNP has been used to switch roles
* so that the "A" device currently acts as A-Peripheral, not A-Host.
* @a_hnp_support: OTG device feature flag, indicating that the A-Host
MORECORE_FAILURE (default: -1)
The value returned upon failure of MORECORE.
MORECORE_CLEARS (default 1)
- True (1) if the routine mapped to MORECORE zeroes out memory (which
+ true (1) if the routine mapped to MORECORE zeroes out memory (which
holds for sbrk).
DEFAULT_TRIM_THRESHOLD
DEFAULT_TOP_PAD
#define SCSI_INT_STATE 0x00010000 /* unknown Interrupt number is stored in 16 LSB */
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
#endif /* _SCSI_H */
#define SCSI_IDENTIFY 0xC0
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
#endif
#if defined(CONFIG_USBD_HS)
/*
* is_usbd_high_speed routine needs to be defined by specific gadget driver
- * It returns TRUE if device enumerates at High speed
- * Retuns FALSE otherwise
+ * It returns true if device enumerates at High speed
+ * Retuns false otherwise
*/
int is_usbd_high_speed(void);
#endif
#endif
} connection_info_t;
-#ifndef BOOL_WAS_DEFINED
-#define BOOL_WAS_DEFINED
-typedef unsigned int bool;
-#endif
-
-#define false 0
-#define true 1
-
#endif
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