]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
rockchip: rk3188: Add Radxa Rock board
authorHeiko Stübner <heiko@sntech.de>
Sun, 26 Mar 2017 19:09:55 +0000 (21:09 +0200)
committerSimon Glass <sjg@chromium.org>
Wed, 5 Apr 2017 02:01:57 +0000 (20:01 -0600)
The Rock is a RK3188 based single board computer by Radxa.
Currently it still relies on the proprietary DDR init and
cannot use the generic SPL, but at least is able to boot
a linux kernel and system up to a regular login prompt.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix sort order in defconfig, enable CONFIG_SPL_TINY_MEMSET:
Signed-off-by: Simon Glass <sjg@chromium.org>
arch/arm/dts/Makefile
arch/arm/dts/rk3188-radxarock.dts [new file with mode: 0644]
arch/arm/mach-rockchip/rk3188/Kconfig
board/radxa/rock/Kconfig [new file with mode: 0644]
board/radxa/rock/MAINTAINERS [new file with mode: 0644]
board/radxa/rock/Makefile [new file with mode: 0644]
board/radxa/rock/rock.c [new file with mode: 0644]
configs/rock_defconfig [new file with mode: 0644]
include/configs/rock.h [new file with mode: 0644]

index 462c690946cb12e7ed84396c23f899bd5a0c4f22..e6f256e5e64f0a3399de1ef2b8456d9f164127b0 100644 (file)
@@ -29,6 +29,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
        rk3036-sdk.dtb \
+       rk3188-radxarock.dtb \
        rk3288-firefly.dtb \
        rk3288-veyron-jerry.dtb \
        rk3288-veyron-mickey.dtb \
diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts
new file mode 100644 (file)
index 0000000..5f5b5e9
--- /dev/null
@@ -0,0 +1,382 @@
+/*
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "rk3188.dtsi"
+
+/ {
+       model = "Radxa Rock";
+       compatible = "radxa,rock", "rockchip,rk3188";
+
+       chosen {
+/*             stdout-path = &uart2; */
+               stdout-path = "serial2:115200n8";
+       };
+
+       config {
+               u-boot,dm-pre-reloc;
+               u-boot,boot-led = "rock:red:power";
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x60000000 0x80000000>;
+       };
+
+       gpio-keys {
+               compatible = "gpio-keys";
+               autorepeat;
+
+               power {
+                       gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_POWER>;
+                       label = "GPIO Key Power";
+                       linux,input-type = <1>;
+                       wakeup-source;
+                       debounce-interval = <100>;
+               };
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+
+               green {
+                       label = "rock:green:user1";
+                       gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+                       default-state = "off";
+               };
+
+               blue {
+                       label = "rock:blue:user2";
+                       gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+                       default-state = "off";
+               };
+
+               sleep {
+                       label = "rock:red:power";
+                       gpios = <&gpio0 15 0>;
+                       default-state = "off";
+               };
+       };
+
+       sound {
+               compatible = "simple-audio-card";
+               simple-audio-card,name = "SPDIF";
+
+               simple-audio-card,dai-link@1 {  /* S/PDIF - S/PDIF */
+                       cpu { sound-dai = <&spdif>; };
+                       codec { sound-dai = <&spdif_out>; };
+               };
+       };
+
+       spdif_out: spdif-out {
+               compatible = "linux,spdif-dit";
+               #sound-dai-cells = <0>;
+       };
+
+       ir_recv: gpio-ir-receiver {
+               compatible = "gpio-ir-receiver";
+               gpios = <&gpio0 10 1>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&ir_recv_pin>;
+       };
+
+       vcc_otg: usb-otg-regulator {
+               compatible = "regulator-fixed";
+               enable-active-high;
+               gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&otg_vbus_drv>;
+               regulator-name = "otg-vbus";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+               regulator-boot-on;
+       };
+
+       vcc_sd0: sdmmc-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "sdmmc-supply";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio3 1 GPIO_ACTIVE_LOW>;
+               startup-delay-us = <100000>;
+               vin-supply = <&vcc_io>;
+       };
+
+       vcc_host: usb-host-regulator {
+               compatible = "regulator-fixed";
+               enable-active-high;
+               gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&host_vbus_drv>;
+               regulator-name = "host-pwr";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-always-on;
+               regulator-boot-on;
+       };
+
+       vsys: vsys-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "vsys";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-boot-on;
+       };
+};
+
+&dmc {
+       rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6
+               0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4
+               0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0
+               0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0
+               0x4 0x0>;
+       rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00
+               0x220 0x40 0x0 0x0>;
+       rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>;
+};
+
+&emac {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+
+       phy = <&phy0>;
+       phy-supply = <&vcc_rmii>;
+
+       phy0: ethernet-phy@0 {
+               reg = <0>;
+               interrupt-parent = <&gpio3>;
+               interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+       };
+};
+
+&cpu0 {
+       cpu0-supply = <&vdd_arm>;
+};
+
+&i2c1 {
+       status = "okay";
+       clock-frequency = <400000>;
+
+       rtc@51 {
+               compatible = "haoyu,hym8563";
+               reg = <0x51>;
+               interrupt-parent = <&gpio0>;
+               interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&rtc_int>;
+               #clock-cells = <0>;
+               clock-output-names = "xin32k";
+       };
+
+       act8846: act8846@5a {
+               compatible = "active-semi,act8846";
+               reg = <0x5a>;
+               status = "okay";
+               system-power-controller;
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&act8846_dvs0_ctl>;
+
+               vp1-supply = <&vsys>;
+               vp2-supply = <&vsys>;
+               vp3-supply = <&vsys>;
+               vp4-supply = <&vsys>;
+               inl1-supply = <&vcc_io>;
+               inl2-supply = <&vsys>;
+               inl3-supply = <&vsys>;
+
+               regulators {
+                       vcc_ddr: REG1 {
+                               regulator-name = "VCC_DDR";
+                               regulator-min-microvolt = <1200000>;
+                               regulator-max-microvolt = <1200000>;
+                               regulator-always-on;
+                       };
+
+                       vdd_log: REG2 {
+                               regulator-name = "VDD_LOG";
+                               regulator-min-microvolt = <1000000>;
+                               regulator-max-microvolt = <1000000>;
+                               regulator-always-on;
+                       };
+
+                       vdd_arm: REG3 {
+                               regulator-name = "VDD_ARM";
+                               regulator-min-microvolt = <875000>;
+                               regulator-max-microvolt = <1350000>;
+                               regulator-always-on;
+                       };
+
+                       vcc_io: REG4 {
+                               regulator-name = "VCC_IO";
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vdd_10: REG5 {
+                               regulator-name = "VDD_10";
+                               regulator-min-microvolt = <1000000>;
+                               regulator-max-microvolt = <1000000>;
+                               regulator-always-on;
+                       };
+
+                       vdd_hdmi: REG6 {
+                               regulator-name = "VDD_HDMI";
+                               regulator-min-microvolt = <2500000>;
+                               regulator-max-microvolt = <2500000>;
+                               regulator-always-on;
+                       };
+
+                       vcc18: REG7 {
+                               regulator-name = "VCC_18";
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
+                       };
+
+                       vcca_33: REG8 {
+                               regulator-name = "VCCA_33";
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vcc_rmii: REG9 {
+                               regulator-name = "VCC_RMII";
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                       };
+
+                       vccio_wl: REG10 {
+                               regulator-name = "VCCIO_WL";
+                               regulator-min-microvolt = <3300000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vcc_18: REG11 {
+                               regulator-name = "VCC18_IO";
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-always-on;
+                       };
+
+                       vcc28: REG12 {
+                               regulator-name = "VCC_28";
+                               regulator-min-microvolt = <2800000>;
+                               regulator-max-microvolt = <2800000>;
+                               regulator-always-on;
+                       };
+               };
+       };
+};
+
+&mmc0 {
+       num-slots = <1>;
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
+       vmmc-supply = <&vcc_sd0>;
+
+       bus-width = <4>;
+       cap-mmc-highspeed;
+       cap-sd-highspeed;
+       disable-wp;
+};
+
+&pwm1 {
+       status = "okay";
+};
+
+&pwm2 {
+       status = "okay";
+};
+
+&pwm3 {
+       status = "okay";
+};
+
+&pinctrl {
+       pcfg_output_low: pcfg-output-low {
+               output-low;
+       };
+
+       act8846 {
+               act8846_dvs0_ctl: act8846-dvs0-ctl {
+                       rockchip,pins = <RK_GPIO3 27 RK_FUNC_GPIO &pcfg_output_low>;
+               };
+       };
+
+       hym8563 {
+               rtc_int: rtc-int {
+                       rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+
+       lan8720a  {
+               phy_int: phy-int {
+                       rockchip,pins = <RK_GPIO3 26 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+       };
+
+       ir-receiver {
+               ir_recv_pin: ir-recv-pin {
+                       rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
+       usb {
+               host_vbus_drv: host-vbus-drv {
+                       rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+               otg_vbus_drv: otg-vbus-drv {
+                       rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+};
+
+&spdif {
+       status = "okay";
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};
+
+&uart2 {
+       status = "okay";
+       u-boot,dm-spl;
+};
+
+&uart3 {
+       status = "okay";
+};
+
+&usbphy {
+       status = "okay";
+};
+
+&usb_host {
+       status = "okay";
+};
+
+&usb_otg {
+       status = "okay";
+};
+
+&wdt {
+       status = "okay";
+};
index b70d45cd624107c87beec2af13340b8340b0d379..d129fcda99dced1fbb53042cd32444814c480130 100644 (file)
@@ -1,5 +1,14 @@
 if ROCKCHIP_RK3188
 
+config TARGET_ROCK
+       bool "Radxa Rock"
+       help
+         Rock is a RK3188-based development board with 2 USB and 1 otg
+         ports, HDMI, TV-out, micro-SD card, audio, WiFi  and 100MBit
+         Ethernet, It also includes on-board nand and 1GB of SDRAM.
+         Expansion connectors provide access to display pins, I2C, SPI,
+         UART and GPIOs.
+
 config SYS_SOC
        default "rockchip"
 
@@ -24,4 +33,6 @@ config TPL_LIBGENERIC_SUPPORT
 config TPL_SERIAL_SUPPORT
        default y
 
+source "board/radxa/rock/Kconfig"
+
 endif
diff --git a/board/radxa/rock/Kconfig b/board/radxa/rock/Kconfig
new file mode 100644 (file)
index 0000000..855b9b6
--- /dev/null
@@ -0,0 +1,15 @@
+if TARGET_ROCK
+
+config SYS_BOARD
+       default "rock"
+
+config SYS_VENDOR
+       default "radxa"
+
+config SYS_CONFIG_NAME
+       default "rock"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
+
+endif
diff --git a/board/radxa/rock/MAINTAINERS b/board/radxa/rock/MAINTAINERS
new file mode 100644 (file)
index 0000000..c5f59c0
--- /dev/null
@@ -0,0 +1,6 @@
+RADXA_ROCK
+M:     Heiko Stuebner <heiko@sntech.de>
+S:     Maintained
+F:     board/radxa/rock
+F:     include/configs/rock.h
+F:     configs/rock_defconfig
diff --git a/board/radxa/rock/Makefile b/board/radxa/rock/Makefile
new file mode 100644 (file)
index 0000000..fe94b60
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Heiko Stuebner
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += rock.o
diff --git a/board/radxa/rock/rock.c b/board/radxa/rock/rock.c
new file mode 100644 (file)
index 0000000..5119e95
--- /dev/null
@@ -0,0 +1,7 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
new file mode 100644 (file)
index 0000000..20a065a
--- /dev/null
@@ -0,0 +1,51 @@
+CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3188=y
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_TARGET_ROCK=y
+CONFIG_SPL_STACK_R_ADDR=0x60080000
+CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_OF_PLATDATA=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+# CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_ROCKCHIP_RK3188_PINCTRL=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_PMIC_ACT8846=y
+CONFIG_REGULATOR_ACT8846=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_RAM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x20064000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
diff --git a/include/configs/rock.h b/include/configs/rock.h
new file mode 100644 (file)
index 0000000..de5291c
--- /dev/null
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3188_common.h>
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+/* SPL @ 32k for 34k
+ * u-boot directly after @ 68k for 400k or so
+ * ENV @ 992k
+ */
+#define CONFIG_ENV_OFFSET ((1024-32) * 1024)
+#else
+/* SPL @ 32k for ~36k
+ * ENV @ 96k
+ * u-boot @ 128K
+ */
+#define CONFIG_ENV_OFFSET (96 * 1024)
+#endif
+
+#endif