ARM: uniphier: rework struct uniphier_board_data

This commit reworks "struct uniphier_board_data" with an array of
DRAM channel data in it.  It will allow further cleanups by means of
"for" statements that iterate over the DDR channels.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c
index f82c7d1f8eac0a96108609fdc29d6d328fd19bdc..bbe8a74ce30ae540dd4c692337296c32839995cb 100644 (file)
--- a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c
@@ -22,7 +22,7 @@ int ph1_ld4_bcu_init(const struct uniphier_board_data *bd)
        writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
 
        /* Specify DDR channel */
-       shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4;
+       shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
        writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
 
        shift -= 32;

diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c
index 75ccd155b0d908b3cd0fafc4f7f2cc2d98af6fd9..b7497e9e5755d5eaad9d936b03f51c6ee49dcb2c 100644 (file)
--- a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c
+++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c
@@ -26,7 +26,7 @@ int ph1_sld3_bcu_init(const struct uniphier_board_data *bd)
        writel(0x24440000, BCSCR5);
 
        /* Specify DDR channel */
-       shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4;
+       shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
        writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
 
        shift -= 32;

diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index d70c7122062110e1c71c1a299c366ecfff1f726b..05b7c7612eaad23e00ca1c65325b48407c4d5b48 100644 (file)
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -14,106 +14,152 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
 static const struct uniphier_board_data ph1_sld3_data = {
-       .dram_ch0_base  = 0x80000000,
-       .dram_ch0_size  = 0x20000000,
-       .dram_ch0_width = 32,
-       .dram_ch1_base  = 0xc0000000,
-       .dram_ch1_size  = 0x20000000,
-       .dram_ch1_width = 16,
-       .dram_ch2_base  = 0xc0000000,
-       .dram_ch2_size  = 0x10000000,
-       .dram_ch2_width = 16,
-       .dram_freq      = 1600,
+       .dram_freq = 1600,
+       .dram_nr_ch = 3,
+       .dram_ch[0] = {
+               .base = 0x80000000,
+               .size = 0x20000000,
+               .width = 32,
+       },
+       .dram_ch[1] = {
+               .base = 0xc0000000,
+               .size = 0x20000000,
+               .width = 16,
+       },
+       .dram_ch[2] = {
+               .base = 0xc0000000,
+               .size = 0x10000000,
+               .width = 16,
+       },
 };
 #endif
 
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
 static const struct uniphier_board_data ph1_ld4_data = {
-       .dram_ch0_base  = 0x80000000,
-       .dram_ch0_size  = 0x10000000,
-       .dram_ch0_width = 16,
-       .dram_ch1_base  = 0x90000000,
-       .dram_ch1_size  = 0x10000000,
-       .dram_ch1_width = 16,
-       .dram_freq      = 1600,
+       .dram_freq = 1600,
+       .dram_nr_ch = 2,
+       .dram_ch[0] = {
+               .base = 0x80000000,
+               .size = 0x10000000,
+               .width = 16,
+       },
+       .dram_ch[1] = {
+               .base = 0x90000000,
+               .size = 0x10000000,
+               .width = 16,
+       },
 };
 #endif
 
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
 /* 1GB RAM board */
 static const struct uniphier_board_data ph1_pro4_data = {
-       .dram_ch0_base  = 0x80000000,
-       .dram_ch0_size  = 0x20000000,
-       .dram_ch0_width = 32,
-       .dram_ch1_base  = 0xa0000000,
-       .dram_ch1_size  = 0x20000000,
-       .dram_ch1_width = 32,
-       .dram_freq      = 1600,
+       .dram_freq = 1600,
+       .dram_nr_ch = 2,
+       .dram_ch[0] = {
+               .base = 0x80000000,
+               .size = 0x20000000,
+               .width = 32,
+       },
+       .dram_ch[1] = {
+               .base = 0xa0000000,
+               .size = 0x20000000,
+               .width = 32,
+       },
 };
 
 /* 2GB RAM board */
 static const struct uniphier_board_data ph1_pro4_2g_data = {
-       .dram_ch0_base  = 0x80000000,
-       .dram_ch0_size  = 0x40000000,
-       .dram_ch0_width = 32,
-       .dram_ch1_base  = 0xc0000000,
-       .dram_ch1_size  = 0x40000000,
-       .dram_ch1_width = 32,
-       .dram_freq      = 1600,
+       .dram_freq = 1600,
+       .dram_nr_ch = 2,
+       .dram_ch[0] = {
+               .base = 0x80000000,
+               .size = 0x40000000,
+               .width = 32,
+       },
+       .dram_ch[1] = {
+               .base = 0xc0000000,
+               .size = 0x40000000,
+               .width = 32,
+       },
 };
 #endif
 
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
 static const struct uniphier_board_data ph1_sld8_data = {
-       .dram_ch0_base  = 0x80000000,
-       .dram_ch0_size  = 0x10000000,
-       .dram_ch0_width = 16,
-       .dram_ch1_base  = 0x90000000,
-       .dram_ch1_size  = 0x10000000,
-       .dram_ch1_width = 16,
-       .dram_freq      = 1333,
+       .dram_freq = 1333,
+       .dram_nr_ch = 2,
+       .dram_ch[0] = {
+               .base = 0x80000000,
+               .size = 0x10000000,
+               .width = 16,
+       },
+       .dram_ch[1] = {
+               .base = 0x90000000,
+               .size = 0x10000000,
+               .width = 16,
+       },
 };
 #endif
 
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
 static const struct uniphier_board_data ph1_pro5_data = {
-       .dram_ch0_base  = 0x80000000,
-       .dram_ch0_size  = 0x20000000,
-       .dram_ch0_width = 32,
-       .dram_ch1_base  = 0xa0000000,
-       .dram_ch1_size  = 0x20000000,
-       .dram_ch1_width = 32,
-       .dram_freq      = 1866,
+       .dram_freq = 1866,
+       .dram_nr_ch = 2,
+       .dram_ch[0] = {
+               .base = 0x80000000,
+               .size = 0x20000000,
+               .width = 32,
+       },
+       .dram_ch[1] = {
+               .base = 0xa0000000,
+               .size = 0x20000000,
+               .width = 32,
+       },
 };
 #endif
 
 #if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
 static const struct uniphier_board_data proxstream2_data = {
-       .dram_ch0_base  = 0x80000000,
-       .dram_ch0_size  = 0x40000000,
-       .dram_ch0_width = 32,
-       .dram_ch1_base  = 0xc0000000,
-       .dram_ch1_size  = 0x20000000,
-       .dram_ch1_width = 32,
-       .dram_ch2_base  = 0xe0000000,
-       .dram_ch2_size  = 0x20000000,
-       .dram_ch2_width = 16,
-       .dram_freq      = 2133,
+       .dram_freq = 2133,
+       .dram_nr_ch = 3,
+       .dram_ch[0] = {
+               .base = 0x80000000,
+               .size = 0x40000000,
+               .width = 32,
+       },
+       .dram_ch[1] = {
+               .base = 0xc0000000,
+               .size = 0x20000000,
+               .width = 32,
+       },
+       .dram_ch[2] = {
+               .base = 0xe0000000,
+               .size = 0x20000000,
+               .width = 16,
+       },
 };
 #endif
 
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
 static const struct uniphier_board_data ph1_ld6b_data = {
-       .dram_ch0_base  = 0x80000000,
-       .dram_ch0_size  = 0x40000000,
-       .dram_ch0_width = 32,
-       .dram_ch1_base  = 0xc0000000,
-       .dram_ch1_size  = 0x20000000,
-       .dram_ch1_width = 32,
-       .dram_ch2_base  = 0xe0000000,
-       .dram_ch2_size  = 0x20000000,
-       .dram_ch2_width = 16,
-       .dram_freq      = 1866,
+       .dram_freq = 1866,
+       .dram_nr_ch = 3,
+       .dram_ch[0] = {
+               .base = 0x80000000,
+               .size = 0x40000000,
+               .width = 32,
+       },
+       .dram_ch[1] = {
+               .base = 0xc0000000,
+               .size = 0x20000000,
+               .width = 32,
+       },
+       .dram_ch[2] = {
+               .base = 0xe0000000,
+               .size = 0x20000000,
+               .width = 16,
+       },
 };
 #endif
 

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
index ffd7aa97b28fe5fcdbcc51c931ffef0b2eacb667..f2889c0f49e00419e6881b7db7ecc76e50dd3a8d 100644 (file)
--- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
@@ -162,13 +162,13 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
 
 int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
 {
-       if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
-           (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
+       if ((bd->dram_ch[0].size == SZ_128M || bd->dram_ch[0].size == SZ_256M) &&
+           (bd->dram_ch[1].size == SZ_128M || bd->dram_ch[1].size == SZ_256M) &&
            (bd->dram_freq == 1333 || bd->dram_freq == 1600) &&
-           bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
+           bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) {
                return umc_init_sub(bd->dram_freq,
-                                   bd->dram_ch0_size / SZ_128M,
-                                   bd->dram_ch1_size / SZ_128M);
+                                   bd->dram_ch[0].size / SZ_128M,
+                                   bd->dram_ch[1].size / SZ_128M);
        } else {
                pr_err("Unsupported DDR configuration\n");
                return -EINVAL;

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
index 261f7cfce7a3a994d948ac7b099f889c5fc36665..16c82645c4694dad99b6d9fdf88c78c4cbcdf0ad 100644 (file)
--- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
@@ -146,39 +146,39 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
 
        writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 
-       ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch0_size);
+       ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size);
 
        ddrphy_prepare_training(phy0_0, 0);
        ddrphy_training(phy0_0);
 
        writel(0x00000103, dramcont0 + UMC_DIOCTLA);
 
-       ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch0_size);
+       ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size);
 
        ddrphy_prepare_training(phy0_1, 1);
        ddrphy_training(phy0_1);
 
        writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 
-       ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch1_size);
+       ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size);
 
        ddrphy_prepare_training(phy1_0, 0);
        ddrphy_training(phy1_0);
 
        writel(0x00000103, dramcont1 + UMC_DIOCTLA);
 
-       ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch1_size);
+       ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size);
 
        ddrphy_prepare_training(phy1_1, 1);
        ddrphy_training(phy1_1);
 
-       ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch0_size,
-                               bd->dram_ch0_width);
+       ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch[0].size,
+                               bd->dram_ch[0].width);
        if (ret)
                return ret;
 
-       ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch1_size,
-                               bd->dram_ch1_width);
+       ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch[1].size,
+                               bd->dram_ch[1].width);
        if (ret)
                return ret;
 

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
index 09f9ccfb43e49fcf1cec865cac8d165b61a741c5..3c2724eb37dd5c23debb45cadcb18f0386ac56ed 100644 (file)
--- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
@@ -142,13 +142,13 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
 
 int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
 {
-       if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
-           (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
+       if ((bd->dram_ch[0].size == SZ_128M || bd->dram_ch[0].size == SZ_256M) &&
+           (bd->dram_ch[1].size == SZ_128M || bd->dram_ch[1].size == SZ_256M) &&
            bd->dram_freq == 1333 &&
-           bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
+           bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) {
                return umc_init_sub(bd->dram_freq,
-                                   bd->dram_ch0_size / SZ_128M,
-                                   bd->dram_ch1_size / SZ_128M);
+                                   bd->dram_ch[0].size / SZ_128M,
+                                   bd->dram_ch[1].size / SZ_128M);
        } else {
                pr_err("Unsupported DDR configuration\n");
                return -EINVAL;

diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c
index 6e7fa885c41e9ab472a113cf14613ae239de0955..6e6fff98e8fd1438946064ddf61d4dcff68d6f2a 100644 (file)
--- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c
+++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c
@@ -603,22 +603,22 @@ int proxstream2_umc_init(const struct uniphier_board_data *bd)
                return -EINVAL;
        }
 
-       ret = umc_init(umc_ch0_base, freq, 0, bd->dram_ch0_size / SZ_256M,
-                      bd->dram_ch0_width);
+       ret = umc_init(umc_ch0_base, freq, 0, bd->dram_ch[0].size / SZ_256M,
+                      bd->dram_ch[0].width);
        if (ret) {
                printf("failed to initialize UMC ch0\n");
                return ret;
        }
 
-       ret = umc_init(umc_ch1_base, freq, 1, bd->dram_ch1_size / SZ_256M,
-                      bd->dram_ch1_width);
+       ret = umc_init(umc_ch1_base, freq, 1, bd->dram_ch[1].size / SZ_256M,
+                      bd->dram_ch[1].width);
        if (ret) {
                printf("failed to initialize UMC ch1\n");
                return ret;
        }
 
-       ret = umc_init(umc_ch2_base, freq, 2, bd->dram_ch2_size / SZ_256M,
-                      bd->dram_ch2_width);
+       ret = umc_init(umc_ch2_base, freq, 2, bd->dram_ch[2].size / SZ_256M,
+                      bd->dram_ch[2].width);
        if (ret) {
                printf("failed to initialize UMC ch2\n");
                return ret;

diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index 0a47e70dcf7de1001183f16b79f15ca6d275ceae..aabd84a8ed63073f862f3993166800f93a3b744f 100644 (file)
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -7,17 +7,18 @@
 #ifndef __MACH_INIT_H
 #define __MACH_INIT_H
 
+#define UNIPHIER_MAX_NR_DRAM_CH                3
+
+struct uniphier_dram_ch {
+       unsigned long base;
+       unsigned long size;
+       unsigned int width;
+};
+
 struct uniphier_board_data {
-       unsigned long dram_ch0_base;
-       unsigned long dram_ch0_size;
-       unsigned long dram_ch0_width;
-       unsigned long dram_ch1_base;
-       unsigned long dram_ch1_size;
-       unsigned long dram_ch1_width;
-       unsigned long dram_ch2_base;
-       unsigned long dram_ch2_size;
-       unsigned long dram_ch2_width;
-       unsigned int  dram_freq;
+       unsigned int dram_freq;
+       unsigned int dram_nr_ch;
+       struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
 };
 
 const struct uniphier_board_data *uniphier_get_board_param(void);

diff --git a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c
index 9718cc560fada941e26ed1f741ba3f708bb76308..6fdf910895765b6b7fbfbe06f7620926cdd77095 100644 (file)
--- a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c
+++ b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c
@@ -21,14 +21,14 @@ int ph1_sld3_memconf_init(const struct uniphier_board_data *bd)
 
        tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
 
-       switch (bd->dram_ch2_width) {
+       switch (bd->dram_ch[2].width) {
        case 16:
                tmp |= SG_MEMCONF_CH2_NUM_1;
-               size_per_word = bd->dram_ch2_size;
+               size_per_word = bd->dram_ch[2].size;
                break;
        case 32:
                tmp |= SG_MEMCONF_CH2_NUM_2;
-               size_per_word = bd->dram_ch2_size >> 1;
+               size_per_word = bd->dram_ch[2].size >> 1;
                break;
        default:
                pr_err("error: unsupported DRAM Ch2 width\n");

diff --git a/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c
index 9a91fb33ef3d3e52efdc75839251637bb8f6d900..c47fe0ae53dd329fe93daf210a75e74a436bd902 100644 (file)
--- a/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c
+++ b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c
@@ -21,14 +21,14 @@ int proxstream2_memconf_init(const struct uniphier_board_data *bd)
 
        tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
 
-       switch (bd->dram_ch2_width) {
+       switch (bd->dram_ch[2].width) {
        case 16:
                tmp |= SG_MEMCONF_CH2_NUM_1;
-               size_per_word = bd->dram_ch2_size;
+               size_per_word = bd->dram_ch[2].size;
                break;
        case 32:
                tmp |= SG_MEMCONF_CH2_NUM_2;
-               size_per_word = bd->dram_ch2_size >> 1;
+               size_per_word = bd->dram_ch[2].size >> 1;
                break;
        default:
                pr_err("error: unsupported DRAM Ch2 width\n");

diff --git a/arch/arm/mach-uniphier/memconf/memconf.c b/arch/arm/mach-uniphier/memconf/memconf.c
index f2a0eaf3f52f64bd4117fc404c374f2e26d4f8e0..3d4b50456b65e254785f3becbe21847e08113708 100644 (file)
--- a/arch/arm/mach-uniphier/memconf/memconf.c
+++ b/arch/arm/mach-uniphier/memconf/memconf.c
@@ -21,14 +21,14 @@ int memconf_init(const struct uniphier_board_data *bd)
 
        tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);
 
-       switch (bd->dram_ch0_width) {
+       switch (bd->dram_ch[0].width) {
        case 16:
                tmp |= SG_MEMCONF_CH0_NUM_1;
-               size_per_word = bd->dram_ch0_size;
+               size_per_word = bd->dram_ch[0].size;
                break;
        case 32:
                tmp |= SG_MEMCONF_CH0_NUM_2;
-               size_per_word = bd->dram_ch0_size >> 1;
+               size_per_word = bd->dram_ch[0].size >> 1;
                break;
        default:
                pr_err("error: unsupported DRAM Ch0 width\n");
@@ -59,14 +59,14 @@ int memconf_init(const struct uniphier_board_data *bd)
 
        tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);
 
-       switch (bd->dram_ch1_width) {
+       switch (bd->dram_ch[1].width) {
        case 16:
                tmp |= SG_MEMCONF_CH1_NUM_1;
-               size_per_word = bd->dram_ch1_size;
+               size_per_word = bd->dram_ch[1].size;
                break;
        case 32:
                tmp |= SG_MEMCONF_CH1_NUM_2;
-               size_per_word = bd->dram_ch1_size >> 1;
+               size_per_word = bd->dram_ch[1].size >> 1;
                break;
        default:
                pr_err("error: unsupported DRAM Ch1 width\n");
@@ -94,7 +94,7 @@ int memconf_init(const struct uniphier_board_data *bd)
                return -EINVAL;
        }
 
-       if (bd->dram_ch0_base + bd->dram_ch0_size < bd->dram_ch1_base)
+       if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
                tmp |= SG_MEMCONF_SPARSEMEM;
        else
                tmp &= ~SG_MEMCONF_SPARSEMEM;