arm64: dts: imx8mp: Add FEC RMII pin mux on i.MX8MP DHCOM

The i.MX8MP DHCOM SoM may come with either external RGMII PHY or
LAN8740Ai RMII PHY on the SoM attached to FEC MAC. Add pin mux
settings for both options, so that DT overlay can override these
settings on SoM variant with the LAN8740Ai PHY.

Signed-off-by: Marek Vasut <marex@denx.de>

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
index 382fbedaf6ba42c28e3ccd9b89aceac73891bfda..ac104cd3e62013324b20d580ba907ac237d6d9fa 100644 (file)
--- a/arch/arm/dts/imx8mp-dhcom-pdk2.dts
+++ b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
@@ -117,7 +117,9 @@
 /delete-node/ &ethphy1f;
 
 &fec { /* Second ethernet */
+       pinctrl-0 = <&pinctrl_fec_rgmii>;
        phy-handle = <&ethphypdk>;
+       phy-mode = "rgmii";
 
        mdio {
                ethphypdk: ethernet-phy@7 { /* KSZ 9021 */

diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi
index b56607dfb395294b4dd55d093db11b0907eae4c3..9fd8bce80656bf0b874d43f4196fa921b24635e6 100644 (file)
--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
@@ -129,9 +129,9 @@
 
 &fec { /* Second ethernet */
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_fec>;
+       pinctrl-0 = <&pinctrl_fec_rmii>;
        phy-handle = <&ethphy1f>;
-       phy-mode = "rgmii";
+       phy-mode = "rmii";
        fsl,magic-packet;
        status = "okay";
 
@@ -723,7 +723,7 @@
                >;
        };
 
-       pinctrl_fec: dhcom-fec-grp {
+       pinctrl_fec_rgmii: dhcom-fec-rgmii-grp {        /* RGMII */
                fsl,pins = <
                        MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK            0x1f
                        MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x3
@@ -744,6 +744,22 @@
                >;
        };
 
+       pinctrl_fec_rmii: dhcom-fec-rmii-grp {  /* RMII */
+               fsl,pins = <
+                       MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x3
+                       MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x3
+                       MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x91
+                       MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x91
+                       MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x91
+                       MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER             0x91
+                       MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x1f
+                       MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x1f
+                       MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x1f
+                       /* Clock */
+                       MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK            0x4000001f
+               >;
+       };
+
        pinctrl_flexcan1: dhcom-flexcan1-grp {
                fsl,pins = <
                        MX8MP_IOMUXC_SPDIF_RX__CAN1_RX                  0x154