net: mvpp2: Enable PHY polling mode on PPv2.2

Testing shows, that PHY polling needs to be enabled on Armada 7k/8k.
Otherwise ethernet transfers will not work correctly. PHY polling
is enabled per default after reset, so we do not need to specifically
enable it, but this makes it clearer.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Chulski <stefanc@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 79442b873e800bb3d7979fed5d51c1560b7cbb91..36e209e83d2f82d0fe4a4cc6bd2345570e77f168 100644 (file)
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4957,14 +4957,15 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
        if (priv->hw_version == MVPP22)
                mvpp2_axi_init(priv);
 
-       /* Disable HW PHY polling */
        if (priv->hw_version == MVPP21) {
+               /* Disable HW PHY polling */
                val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
                val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
                writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
        } else {
+               /* Enable HW PHY polling */
                val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
-               val &= ~MVPP22_SMI_POLLING_EN;
+               val |= MVPP22_SMI_POLLING_EN;
                writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
        }