armv8: fsl-layerscape: Make USB masters snoopable

Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and
SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write
snoop signal on LS1043A and LS1046A.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 3fd34e3a435d232ea2248219a75f02b467be6eda..1f1869e8cf6b5dc409306bc9da86d190e44e46c8 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -627,10 +627,19 @@ void fsl_lsch2_early_init_f(void)
 #endif
 #endif
        /* Make SEC reads and writes snoopable */
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+       setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+                       SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+                       SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+                       SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+                       SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
+                       SCFG_SNPCNFGCR_SATAWRSNP);
+#else
        setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
                     SCFG_SNPCNFGCR_SECWRSNP |
                     SCFG_SNPCNFGCR_SATARDSNP |
                     SCFG_SNPCNFGCR_SATAWRSNP);
+#endif
 
        /*
         * Enable snoop requests and DVM message requests for

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 3a59abb10e5b75e448368818fc596933762048cb..862ec2e2f1f6880e843d55e574195a9a396dcc3a 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -409,6 +409,12 @@ struct ccsr_gur {
 #define SCFG_SNPCNFGCR_SECWRSNP                0x40000000
 #define SCFG_SNPCNFGCR_SATARDSNP       0x00800000
 #define SCFG_SNPCNFGCR_SATAWRSNP       0x00400000
+#define SCFG_SNPCNFGCR_USB1RDSNP       0x00200000
+#define SCFG_SNPCNFGCR_USB1WRSNP       0x00100000
+#define SCFG_SNPCNFGCR_USB2RDSNP       0x00008000
+#define SCFG_SNPCNFGCR_USB2WRSNP       0x00010000
+#define SCFG_SNPCNFGCR_USB3RDSNP       0x00002000
+#define SCFG_SNPCNFGCR_USB3WRSNP       0x00004000
 
 /* RGMIIPCR bit definitions*/
 #define SCFG_RGMIIPCR_EN_AUTO          BIT(3)