riscv: Add exception codes for xcause register

This adds all exception codes in encoding.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>

diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h
index 05e1ce352641be8b4718148ad6ebc2354b7c0077..772668c74e6a840c3fb7beeaf5c6cfc8f9ea115b 100644 (file)
--- a/arch/riscv/include/asm/encoding.h
+++ b/arch/riscv/include/asm/encoding.h
@@ -85,6 +85,21 @@
 #define IRQ_COP                12
 #define IRQ_HOST       13
 
+#define CAUSE_MISALIGNED_FETCH         0
+#define CAUSE_FETCH_ACCESS             1
+#define CAUSE_ILLEGAL_INSTRUCTION      2
+#define CAUSE_BREAKPOINT               3
+#define CAUSE_MISALIGNED_LOAD          4
+#define CAUSE_LOAD_ACCESS              5
+#define CAUSE_MISALIGNED_STORE         6
+#define CAUSE_STORE_ACCESS             7
+#define CAUSE_USER_ECALL               8
+#define CAUSE_SUPERVISOR_ECALL         9
+#define CAUSE_MACHINE_ECALL            11
+#define CAUSE_FETCH_PAGE_FAULT         12
+#define CAUSE_LOAD_PAGE_FAULT          13
+#define CAUSE_STORE_PAGE_FAULT         15
+
 #define DEFAULT_RSTVEC         0x00001000
 #define DEFAULT_NMIVEC         0x00001004
 #define DEFAULT_MTVEC          0x00001010