powerpc/mpc85xx: Add workaround to enable TDM on T1040

This is a workaround for 32 bit hardware limitation of TDM.
T1040 has 36 bit physical addressing, TDM DMAC register
are 32 bit wide but need to store address of CCSR space
which lies beyond 32 bit address range. This workaround
creats a LAW to enable access of TDM DMA to CCSR by
mapping CCSR to overlap with DDR.
A hole of 16M is created in memory using device tree. This
workaround law is set only if "tdm" is defined in hwconfig.
Also disable POST tests and add LIODN for TDM

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index d6cf88555a11d23056caef9d62a58a9b436a2986..78316a681593dd630cd5ef2c402b5ca9dc078ecb 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -225,6 +225,32 @@ static void disable_cpc_sram(void)
 }
 #endif
 
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#ifdef CONFIG_POST
+#error POST memory test cannot be enabled with TDM
+#endif
+static void enable_tdm_law(void)
+{
+       int ret;
+       char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+       int tdm_hwconfig_enabled = 0;
+
+       /*
+        * Extract hwconfig from environment since environment
+        * is not setup properly yet. Search for tdm entry in
+        * hwconfig.
+        */
+       ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+       if (ret > 0) {
+               tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+               /* If tdm is defined in hwconfig, set law for tdm workaround */
+               if (tdm_hwconfig_enabled)
+                       set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
+                                    LAW_TRGT_IF_CCSR);
+       }
+}
+#endif
+
 static void enable_cpc(void)
 {
        int i;
@@ -729,6 +755,9 @@ skip_l2:
        disable_cpc_sram();
 #endif
        enable_cpc();
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+       enable_tdm_law();
+#endif
 
 #ifndef CONFIG_SYS_FSL_NO_SERDES
        /* needs to be in ram since code uses global static vars */

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index ed80a841804425f07c6064c216fd629ee0c3b010..85dfa5bc01e592d502ae27d9afe66bfc0f2cb73f 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -14,6 +14,7 @@
 #include <linux/ctype.h>
 #include <asm/io.h>
 #include <asm/fsl_portals.h>
+#include <hwconfig.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
@@ -35,6 +36,11 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
        u32 bootpg = determine_mp_bootpg(NULL);
        u32 id = get_my_id();
        const char *enable_method;
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+       int ret;
+       int tdm_hwconfig_enabled = 0;
+       char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+#endif
 
        off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
        while (off != -FDT_ERR_NOTFOUND) {
@@ -77,6 +83,26 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
                                "device_type", "cpu", 4);
        }
 
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#define        CONFIG_MEM_HOLE_16M     0x1000000
+       /*
+        * Extract hwconfig from environment.
+        * Search for tdm entry in hwconfig.
+        */
+       ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+       if (ret > 0)
+               tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+
+       /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
+       if (tdm_hwconfig_enabled) {
+               off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
+                                     CONFIG_MEM_HOLE_16M);
+               if (off < 0)
+                       printf("Failed  to reserve memory for tdm: %s\n",
+                              fdt_strerror(off));
+       }
+#endif
+
        /* Reserve the boot page so OSes dont use it */
        if ((u64)bootpg < memory_limit) {
                off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);

diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
index 1034cd4852b5b3bf97a8ab257448453db0774ddf..a5dfb81781879d54438f9331934e9793096cf2b5 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
@@ -47,6 +47,7 @@ struct liodn_id_table liodn_tbl[] = {
 
        /* SET_NEXUS_LIODN(557), -- not yet implemented */
        SET_QE_LIODN(559),
+       SET_TDM_LIODN(560),
 };
 int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
 

diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 37d3a2246166f1adf6b61a8b23550e0ce90d0844..3b504875e0f9db26134751827d5a20dcaa045af0 100644 (file)
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -68,6 +68,7 @@ enum law_trgt_if {
        LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
        LAW_TRGT_IF_BMAN = 0x18,
        LAW_TRGT_IF_DCSR = 0x1d,
+       LAW_TRGT_IF_CCSR = 0x1e,
        LAW_TRGT_IF_LBC = 0x1f,
        LAW_TRGT_IF_QMAN = 0x3c,
 

diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index f658bcbc66ae07396f9bf8adf9bb3e1d20ef42c0..adfbb66e77cf71e64dd87cc0a625400e05172266 100644 (file)
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -103,6 +103,10 @@ extern void fdt_fixup_liodn(void *blob);
        SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
                CONFIG_SYS_MPC85xx_QE_OFFSET)
 
+#define SET_TDM_LIODN(liodn) \
+       SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
+               CONFIG_SYS_MPC85xx_TDM_OFFSET)
+
 #define SET_QMAN_LIODN(liodn) \
        SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
                CONFIG_SYS_FSL_QMAN_OFFSET, \

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index fe1dcc27d6d078d9885a89408c0b9afcce7a3e20..8258ab3805009cd148dd9607a78f5acd556ddef4 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1899,7 +1899,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
        u32     sata2liodnr;    /* SATA 2 LIODN */
        u32     sata3liodnr;    /* SATA 3 LIODN */
        u32     sata4liodnr;    /* SATA 4 LIODN */
-       u8      res22[24];
+       u8      res22[20];
+       u32     tdmliodnr;      /* TDM LIODN */
        u32     qeliodnr;       /* QE LIODN */
        u8      res_57c[4];
        u32     dma1liodnr;     /* DMA 1 LIODN */
@@ -2915,6 +2916,7 @@ struct ccsr_sfp_regs {
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET          0x124000
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET          0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET         0x130000
+#define CONFIG_SYS_MPC85xx_TDM_OFFSET          0x185000
 #define CONFIG_SYS_MPC85xx_QE_OFFSET           0x140000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET     0x1e0000
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\

diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 2215ac86abc2eed58213869ae3a216d28e6881a6..f2a75aed43b0864b9c2ab09610f0fde302e73a9a 100644 (file)
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -201,6 +201,12 @@ unsigned long get_board_ddr_clk(void);
                                CSPR_MSEL_NOR | \
                                CSPR_V)
 #define CONFIG_SYS_NOR_AMASK   IFC_AMASK(128*1024*1024)
+
+/*
+ * TDM Definition
+ */
+#define T1040_TDM_QUIRK_CCSR_BASE      0xfe000000
+
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR    CSOR_NAND_TRHZ_80
 #define CONFIG_SYS_NOR_FTIM0   (FTIM0_NOR_TACSE(0x4) | \

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index e564cb7f53283f3761ed81bba004008ef2d92751..8d6c51bb37bc6b771b2ba62656dfc9b1e9d16053 100644 (file)
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -230,6 +230,12 @@
                                CSPR_MSEL_NOR | \
                                CSPR_V)
 #define CONFIG_SYS_NOR_AMASK   IFC_AMASK(128*1024*1024)
+
+/*
+ * TDM Definition
+ */
+#define T1040_TDM_QUIRK_CCSR_BASE      0xfe000000
+
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR    CSOR_NAND_TRHZ_80
 #define CONFIG_SYS_NOR_FTIM0   (FTIM0_NOR_TACSE(0x4) | \