clk: sunxi: r40: Fix GMAC reset reg offset

GMAC reset reg offset added by below commit seems to assume
it as EMAC but R40 indeed using GMAC.
"clk: sunxi: Implement EMAC, GMAC clocks, resets"
(sha1: 68620c9698f109c1f001f80d282138a5c67cabef)

So, fix by updating the reg offset for RST_BUS_GMAC.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index 30beac98bb88eb998ed03e65b61027c6fbfea786..44abc4f536d2c651fa3c34de20eb95cbff0a5ad0 100644 (file)
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -62,7 +62,6 @@ static struct ccu_reset r40_resets[] = {
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
        [RST_BUS_MMC3]          = RESET(0x2c0, BIT(11)),
-       [RST_BUS_GMAC]          = RESET(0x2c0, BIT(17)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_SPI2]          = RESET(0x2c0, BIT(22)),
@@ -75,6 +74,8 @@ static struct ccu_reset r40_resets[] = {
        [RST_BUS_OHCI1]         = RESET(0x2c0, BIT(30)),
        [RST_BUS_OHCI2]         = RESET(0x2c0, BIT(31)),
 
+       [RST_BUS_GMAC]          = RESET(0x2c4, BIT(17)),
+
        [RST_BUS_UART0]         = RESET(0x2d8, BIT(16)),
        [RST_BUS_UART1]         = RESET(0x2d8, BIT(17)),
        [RST_BUS_UART2]         = RESET(0x2d8, BIT(18)),