video: zynqmp: Enable 1024x768 resolution

Add support for 1024x768 60p resolution and set it up this resolution by
default. This resolution is still able to use only one GT line. But for
example 800x600 60p has some issues with settings. That's why extend this
table by tested resolutions.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/957e1e85a05744326ec2606dadc1af6e69976f37.1684312924.git.michal.simek@amd.com

diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c
index c287b475a8d778f0fe85853fe82540e037de172d..def4dcf6261a4ae36962459ca0faffe8c7c66421 100644 (file)
--- a/drivers/video/zynqmp/zynqmp_dpsub.c
+++ b/drivers/video/zynqmp/zynqmp_dpsub.c
@@ -27,8 +27,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* Maximum supported resolution */
-#define WIDTH                          640
-#define HEIGHT                         480
+#define WIDTH                          1024
+#define HEIGHT                         768
 
 static struct dp_dma dp_dma;
 static struct dp_dma_descriptor cur_desc __aligned(256);
@@ -1995,7 +1995,7 @@ static void init_run_config(struct udevice *dev)
        struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
 
        dp_sub->dp_dma               = &dp_dma;
-       dp_sub->video_mode           = VIDC_VM_640x480_60_P;
+       dp_sub->video_mode           = VIDC_VM_1024x768_60_P;
        dp_sub->bpc                  = VIDC_BPC_8;
        dp_sub->color_encode         = DP_CENC_RGB;
        dp_sub->use_max_cfg_caps     = 1;

diff --git a/drivers/video/zynqmp/zynqmp_dpsub.h b/drivers/video/zynqmp/zynqmp_dpsub.h
index d2a6f1f4c7c8e69b0856e0bf143d2d2d99de5ae3..7d2737e31aac6ee565a5d4fa86ec58376c6037d9 100644 (file)
--- a/drivers/video/zynqmp/zynqmp_dpsub.h
+++ b/drivers/video/zynqmp/zynqmp_dpsub.h
@@ -9,6 +9,7 @@
 
 enum video_mode {
        VIDC_VM_640x480_60_P = 0,
+       VIDC_VM_1024x768_60_P = 1,
 };
 
 enum {
@@ -644,7 +645,7 @@ struct zynqmp_dpsub_priv {
 #define VIDEO_REF_CTRL_DIVISOR0_SHIFT                                  8
 #define PSS_REF_CLK                                                    0
 #define FPD_CTRL_OFFSET                                                        12
-#define VIDC_VM_NUM_SUPPORTED                                          1
+#define VIDC_VM_NUM_SUPPORTED                                          2
 
 static const u32 vs[4][4] = {
        { 0x2a, 0x27, 0x24, 0x20 },
@@ -664,6 +665,9 @@ const struct video_timing_mode vidc_video_timing_modes[VIDC_VM_NUM_SUPPORTED] =
        { VIDC_VM_640x480_60_P, "640x480@60Hz", VIDC_FR_60HZ,
        {640, 16, 96, 48, 800, 0,
         480, 10, 2, 33, 525, 0, 0, 0, 0, 0} },
+       { VIDC_VM_1024x768_60_P, "1024x768@60Hz", VIDC_FR_60HZ,
+       {1024, 24, 136, 160, 1344, 0,
+        768, 3, 6, 29, 806, 0, 0, 0, 0, 0} },
 };
 
 const struct av_buf_vid_attribute avbuf_supported_formats[] = {