powerpc: mpc85xx: Fix static TLB table for SDRAM

Most predefined TLB tables don't have memory coherence bit set for
SDRAM. This wasn't an issue before invalidate_dcache_range() function
was enabled. Without the coherence bit, dcache invalidation doesn't
automatically flush the cache. The coherence bit is already set when
dynamic TLB table is used. For some boards with different SPL boot
method, or with legacy fixed setting, this bit needs to be set in
TLB files.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/board/Arcturus/ucp1020/tlb.c b/board/Arcturus/ucp1020/tlb.c
index fd7134f5cf9c314ebb55c234fd54b41cfd7a5097..95d58af0e5e8167ab0244f592f5886ccd74f2965 100644 (file)
--- a/board/Arcturus/ucp1020/tlb.c
+++ b/board/Arcturus/ucp1020/tlb.c
@@ -79,7 +79,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
        (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
        /* *I*G - eSDHC/eSPI/NAND boot */
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                     MAS3_SX | MAS3_SW | MAS3_SR, 0,
+                     MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
                      0, 8, BOOKE_PAGESZ_1G, 1),
 
 #endif /* RAMBOOT/SPL */

diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
index 7b55b860d088f00a85a3d301dd2bf4cb995552a1..88910d6cd11c87bbe3fa6e06418cdbefc5d30424 100644 (file)
--- a/board/freescale/b4860qds/tlb.c
+++ b/board/freescale/b4860qds/tlb.c
@@ -147,7 +147,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 17, BOOKE_PAGESZ_2G, 1)
 #endif
 };

diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c
index c8ecf5de59190f2fd06ad06cccc266a2ef1db639..e5dab9ea30d21fb07577be0248f0a7d29a92e94b 100644 (file)
--- a/board/freescale/bsc9131rdb/tlb.c
+++ b/board/freescale/bsc9131rdb/tlb.c
@@ -49,7 +49,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if  defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                        0, 8, BOOKE_PAGESZ_1G, 1),
 #endif
 

diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
index 07febc2b375ba1f8ff80003e8f5ee90b23f20457..56199e52449f94388fbbf30129a31a09576cb181 100644 (file)
--- a/board/freescale/bsc9132qds/tlb.c
+++ b/board/freescale/bsc9132qds/tlb.c
@@ -71,7 +71,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 8, BOOKE_PAGESZ_1G, 1),
 #endif
 

diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index c5abed05049b8e7b790ff19bfcdf0be24f993d40..85d58c8cd4580d90f4c8c98b36d367af303d998b 100644 (file)
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -67,11 +67,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
                (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
                        CONFIG_SYS_DDR_SDRAM_BASE,
-                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                        0, 8, BOOKE_PAGESZ_256M, 1),
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
                        CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                        0, 9, BOOKE_PAGESZ_256M, 1),
 #endif
 

diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c
index fff3b4a7c28cd7b066083f010b372b6bd319bd33..6664f2755d380988eeece24601fa91d3cda52e0d 100644 (file)
--- a/board/freescale/mpc8541cds/tlb.c
+++ b/board/freescale/mpc8541cds/tlb.c
@@ -81,7 +81,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * 0xf000_0000  64M     LBC SDRAM
         */
        SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 6, BOOKE_PAGESZ_64M, 1),
 
        /*

diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index 363e043d068e4074ff958c6c0e06760dc1fd06b3..571341ff68eab7faa902d627a31cecf812a5afbd 100644 (file)
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -48,7 +48,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         */
        SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
                      CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 2, BOOKE_PAGESZ_64M, 1),
 
        /*

diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c
index b5e2fec1f995ae26e245cbd89c420abe4e95f943..03d0fa1cd9a6f682ad0ffc7d1959e88e4c1d04f0 100644 (file)
--- a/board/freescale/mpc8568mds/tlb.c
+++ b/board/freescale/mpc8568mds/tlb.c
@@ -67,7 +67,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * 0xf000_0000  64M     LBC SDRAM
         */
        SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 4, BOOKE_PAGESZ_64M, 1),
 
        /*

diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index af40f979d36efb0ff76e20cd6faff65e3c12b55a..7d151f9e5f344bbfc5b8c7bac875e21015114a01 100644 (file)
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -76,7 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #if defined(CONFIG_SYS_RAMBOOT) || \
        (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                        0, 8, BOOKE_PAGESZ_1G, 1),
 #endif
 

diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c
index e7ae2e25b224acf62009cc39760c2b4e36ea5f30..69d5e449e0d46253e42cfa0017f6ca16ab14be19 100644 (file)
--- a/board/freescale/p1022ds/tlb.c
+++ b/board/freescale/p1022ds/tlb.c
@@ -75,12 +75,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
        (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
        /* **** - eSDHC/eSPI/NAND boot */
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 8, BOOKE_PAGESZ_1G, 1),
        /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
                      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 9, BOOKE_PAGESZ_1G, 1),
 #endif
 

diff --git a/board/freescale/p1023rdb/tlb.c b/board/freescale/p1023rdb/tlb.c
index 8fd178e211bacebac7d6fbae4387d66450098c64..35a63fe0269e87a4d16cf207bd5cf872a95148be 100644 (file)
--- a/board/freescale/p1023rdb/tlb.c
+++ b/board/freescale/p1023rdb/tlb.c
@@ -86,12 +86,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #ifdef CONFIG_SYS_RAMBOOT
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
                      CONFIG_SYS_DDR_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 12, BOOKE_PAGESZ_256M, 1),
 
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
                      CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 13, BOOKE_PAGESZ_256M, 1),
 #endif
 };

diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 7cba411007fb8a3c4f0f6f6108e51651abb5a4df..6324ebfa322020367cdb727888f4088e3c5c44e9 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -82,7 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
        (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
        /* *I*G - eSDHC/eSPI/NAND boot */
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                        0, 8, BOOKE_PAGESZ_1G, 1),
 
 #if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)

diff --git a/board/freescale/p1_twr/tlb.c b/board/freescale/p1_twr/tlb.c
index 308335c974a060184f28adc42a789ca2ab0f0d0a..0f365f9163457db662a1bbe358317bad13ea3795 100644 (file)
--- a/board/freescale/p1_twr/tlb.c
+++ b/board/freescale/p1_twr/tlb.c
@@ -67,7 +67,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #ifdef CONFIG_SYS_RAMBOOT
        /* *I*G - eSDHC boot */
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                        0, 8, BOOKE_PAGESZ_1G, 1),
 #endif
 

diff --git a/board/freescale/t102xqds/tlb.c b/board/freescale/t102xqds/tlb.c
index 409e1739996c4847040ceb110d29abdcc7060590..0d27a998c51a410999efa912d073ebceb29a13f9 100644 (file)
--- a/board/freescale/t102xqds/tlb.c
+++ b/board/freescale/t102xqds/tlb.c
@@ -102,11 +102,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 12, BOOKE_PAGESZ_1G, 1),
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
                      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 13, BOOKE_PAGESZ_1G, 1)
 #endif
        /* entry 14 and 15 has been used hard coded, they will be disabled

diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c
index 8269b3d72505c91d9ee83e091c81affe1507bb81..d77ce25784cea8fd68558fb94be26828ffccc009 100644 (file)
--- a/board/freescale/t102xrdb/tlb.c
+++ b/board/freescale/t102xrdb/tlb.c
@@ -102,11 +102,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 12, BOOKE_PAGESZ_1G, 1),
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
                      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 13, BOOKE_PAGESZ_1G, 1)
 #endif
        /* entry 14 and 15 has been used hard coded, they will be disabled

diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
index 7c0511e268bad96546b13aae3882a0e1f7dd3275..078947902fd952b1f2eee3cd25d3bc87deaa7553 100644 (file)
--- a/board/freescale/t104xrdb/tlb.c
+++ b/board/freescale/t104xrdb/tlb.c
@@ -120,11 +120,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 12, BOOKE_PAGESZ_1G, 1),
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
                      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 13, BOOKE_PAGESZ_1G, 1)
 #endif
 };

diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c
index 8d602989b2dd92b1ce78f31db2aa04cdc461d637..b0b3b4d48a5435e26fe230c9a959e79eceb5c8f2 100644 (file)
--- a/board/freescale/t208xqds/tlb.c
+++ b/board/freescale/t208xqds/tlb.c
@@ -145,7 +145,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 19, BOOKE_PAGESZ_2G, 1)
 #endif
 };

diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
index 2ebea36a5c22d5664c3fea4129f347bb8b6bc2af..2cae4d02b36586f197735c08a7a4dfda4b6bf3fd 100644 (file)
--- a/board/freescale/t208xrdb/tlb.c
+++ b/board/freescale/t208xrdb/tlb.c
@@ -144,7 +144,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #endif
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 19, BOOKE_PAGESZ_2G, 1)
 #endif
 

diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
index 1e4d096f5f9716649a23a7eabb48f976bd10f1ef..a6d8bb36037d2a28f291a00eeba4e0dc3083e1fb 100644 (file)
--- a/board/freescale/t4qds/tlb.c
+++ b/board/freescale/t4qds/tlb.c
@@ -139,7 +139,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 19, BOOKE_PAGESZ_2G, 1)
 #endif
 };

diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c
index 6a6b4b5cc13feaee680d9083e6e9fa1caa312e9e..648cfabeea0a8260aa64d2149d1752edf40685c1 100644 (file)
--- a/board/freescale/t4rdb/tlb.c
+++ b/board/freescale/t4rdb/tlb.c
@@ -116,7 +116,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #endif
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 18, BOOKE_PAGESZ_2G, 1)
 #endif
 };

diff --git a/board/gdsys/p1022/tlb.c b/board/gdsys/p1022/tlb.c
index aee86a4356d6876f3b7a42b60882af3e69f6c043..58b438fc1493ca2883f9ec9815ae36d9aeeb2c80 100644 (file)
--- a/board/gdsys/p1022/tlb.c
+++ b/board/gdsys/p1022/tlb.c
@@ -65,7 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #ifdef CONFIG_SYS_RAMBOOT
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 6, BOOKE_PAGESZ_1G, 1),
 #endif
 #endif

diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index 2f7e4c536488150529f660fef1943ff44324f67a..d2bf3049f10a1a810803214fb48da5be61099903 100644 (file)
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -66,7 +66,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * 0xf0000000   64M     LBC SDRAM First half
         */
        SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 3, BOOKE_PAGESZ_64M, 1),
 
        /*
@@ -75,7 +75,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         */
        SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
                      CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
-                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 4, BOOKE_PAGESZ_64M, 1),
 #endif