serial: pl01x: fix pl011 baud rate configuration

UART_IBRD, UART_FBRD, and UART_LCR_H form a single 30-bit wide register which
is updated on a single write strobe generated by a UART_LCR_H write. So, to
internally update the content of UART_IBRD or UART_FBRD, a write to UART_LCR_H
must always be performed at the end.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 1860289ce4e781a81b76eab6f18aabd655e3dc4a..a58ad8ab36bebd1afb5970365489732c7a6699f6 100644 (file)
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -122,6 +122,7 @@ static int pl01x_generic_serial_init(struct pl01x_regs *regs,
 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
                                int clock, int baudrate)
 {
+       unsigned int lcr;
        switch (type) {
        case TYPE_PL010: {
                unsigned int divisor;
@@ -175,6 +176,13 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
                writel(divider, &regs->pl011_ibrd);
                writel(fraction, &regs->pl011_fbrd);
 
+               /*
+                * Internal update of baud rate register require line
+                * control register write
+                */
+               lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
+               writel(lcr, &regs->pl011_lcrh);
+
                /* Finally, enable the UART */
                writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
                       UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);