configs: stm32mp1: reduce DDR_CACHEABLE_SIZE to supported 256MB DDR

Reduces the CONFIG_DDR_CACHEABLE_SIZE, the size of DDR mapped cacheable
before relocation, to support DDR with only 256MB because the OP-TEE
reserved memory is located at end of the DDR.

By default the new size of 128MB cacheable memory is enough
in dram_bank_mmu_setup() for early_enable_caches() in arch_cpu_init()
and is correct for DDR size = 256MB.

After relocation the real size of DDR, excluding the no-map reserved
memory, is used after the U-Boot device tree parsing.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig
index 5e9abc5e262569526cc9cd78d6a587b443dc149b..82b62744f6db336e5c3c04b610e52ad9a5ba1b84 100644 (file)
--- a/configs/stm32mp13_defconfig
+++ b/configs/stm32mp13_defconfig
@@ -7,7 +7,7 @@ CONFIG_ENV_OFFSET=0x900000
 CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dk"
 CONFIG_SYS_PROMPT="STM32MP> "
 CONFIG_STM32MP13x=y
-CONFIG_DDR_CACHEABLE_SIZE=0x10000000
+CONFIG_DDR_CACHEABLE_SIZE=0x8000000
 CONFIG_CMD_STM32KEY=y
 CONFIG_TARGET_ST_STM32MP13x=y
 CONFIG_ENV_OFFSET_REDUND=0x940000

diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig
index 12b9b549732e96079924c97985e3502269883750..2700b5c49910a4e5ba48cfd8b3f14987b9567fdf 100644 (file)
--- a/configs/stm32mp15_defconfig
+++ b/configs/stm32mp15_defconfig
@@ -7,7 +7,7 @@ CONFIG_ENV_OFFSET=0x900000
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
 CONFIG_SYS_PROMPT="STM32MP> "
-CONFIG_DDR_CACHEABLE_SIZE=0x10000000
+CONFIG_DDR_CACHEABLE_SIZE=0x8000000
 CONFIG_CMD_STM32KEY=y
 CONFIG_TYPEC_STUSB160X=y
 CONFIG_TARGET_ST_STM32MP15x=y