]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
mtd: spi-nor-core: Add support for Read/Write Any Register
authorTakahiro Kuwano <Takahiro.Kuwano@infineon.com>
Tue, 29 Jun 2021 06:00:58 +0000 (15:00 +0900)
committerJagan Teki <jagan@amarulasolutions.com>
Tue, 29 Jun 2021 13:46:54 +0000 (19:16 +0530)
Some of Spansion/Cypress chips support Read/Write Any Register commands.
These commands are mainly used to write volatile registers and access to
the registers in second and subsequent die for multi-die package parts.

The Read Any Register instruction (65h) is followed by register address
and dummy cycles, then the selected register byte is returned.

The Write Any Register instruction (71h) is followed by register address
and register byte to write.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
drivers/mtd/spi/spi-nor-core.c
include/linux/mtd/spi-nor.h

index 8dd44c0f1e1bfd39b3412982dc45b6b6c5064d6e..9e85f7d73e00b486b5004226a238f10fa07682ef 100644 (file)
@@ -315,6 +315,31 @@ static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
        return spi_nor_read_write_reg(nor, &op, buf);
 }
 
+#ifdef CONFIG_SPI_FLASH_SPANSION
+static int spansion_read_any_reg(struct spi_nor *nor, u32 addr, u8 dummy,
+                                u8 *val)
+{
+       struct spi_mem_op op =
+                       SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDAR, 1),
+                                  SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
+                                  SPI_MEM_OP_DUMMY(dummy / 8, 1),
+                                  SPI_MEM_OP_DATA_IN(1, NULL, 1));
+
+       return spi_nor_read_write_reg(nor, &op, val);
+}
+
+static int spansion_write_any_reg(struct spi_nor *nor, u32 addr, u8 val)
+{
+       struct spi_mem_op op =
+                       SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRAR, 1),
+                                  SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
+                                  SPI_MEM_OP_NO_DUMMY,
+                                  SPI_MEM_OP_DATA_OUT(1, NULL, 1));
+
+       return spi_nor_read_write_reg(nor, &op, &val);
+}
+#endif
+
 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
                                 u_char *buf)
 {
index 95ea6eb27a648ac8912373e6b8452f8a1056c7aa..5bb06882ea5de06388570a7446995c0c8be52fcc 100644 (file)
 #define SPINOR_OP_BRWR         0x17    /* Bank register write */
 #define SPINOR_OP_BRRD         0x16    /* Bank register read */
 #define SPINOR_OP_CLSR         0x30    /* Clear status register 1 */
+#define SPINOR_OP_RDAR         0x65    /* Read any register */
+#define SPINOR_OP_WRAR         0x71    /* Write any register */
 
 /* Used for Micron flashes only. */
 #define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */