clk: rockchip: rk3328: Configure CPU clock

Add a call to rk3328_configure_cpu() during initialization to set the
CPU-clock frequency.

Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
index 15b9788d9c4a24dd8bb0cd7fcf6e75c7faba1050..4bf69dbe08868c88c8ccbb7b4ea3d0e72dfa7a49 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
@@ -66,4 +66,7 @@ enum apll_frequencies {
        APLL_600_MHZ,
 };
 
+void rk3328_configure_cpu(struct rk3328_cru *cru,
+                         enum apll_frequencies apll_freq);
+
 #endif /* __ASM_ARCH_CRU_RK3328_H_ */

diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index a89e2ecc4ad6651cc73764448eb261d2a2d6a5e6..4331048a87612113bf3f2a684eccc21e32e05782 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -282,6 +282,8 @@ static void rkclk_init(struct rk3328_cru *cru)
        u32 hclk_div;
        u32 pclk_div;
 
+       rk3328_configure_cpu(cru, APLL_600_MHZ);
+
        /* configure gpll cpll */
        rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
        rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);