riscv: delay initialization of caches and debug UART

Move the initialization of the caches and the debug UART until after
board_init_f_init_reserve. This is in preparation for SMP support, where
code prior to this point will be executed by all harts. This ensures
that initialization will only be performed once on the main hart running
U-Boot.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 81ea52b170f7f898e56b32c2ace08a602609ecf8..a30f6f7194772c46e158c016a1e0b7d71a004d52 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -45,10 +45,6 @@ _start:
        /* mask all interrupts */
        csrw    MODE_PREFIX(ie), zero
 
-       /* Enable cache */
-       jal     icache_enable
-       jal     dcache_enable
-
 /*
  * Set stackpointer in internal/ex RAM to call board_init_f
  */
@@ -57,10 +53,6 @@ call_board_init_f:
        li      t1, CONFIG_SYS_INIT_SP_ADDR
        and     sp, t1, t0              /* force 16 byte alignment */
 
-#ifdef CONFIG_DEBUG_UART
-       jal     debug_uart_init
-#endif
-
 call_board_init_f_0:
        mv      a0, sp
        jal     board_init_f_alloc_reserve
@@ -74,6 +66,14 @@ call_board_init_f_0:
        /* save the boot hart id to global_data */
        SREG    s0, GD_BOOT_HART(gp)
 
+       /* Enable cache */
+       jal     icache_enable
+       jal     dcache_enable
+
+#ifdef CONFIG_DEBUG_UART
+       jal     debug_uart_init
+#endif
+
        mv      a0, zero                /* a0 <-- boot_flags = 0 */
        la      t5, board_init_f
        jr      t5                      /* jump to board_init_f() */