spi: cadence_qspi: setup ADDR Bits in cmd reads

Setup the Addr bit field while issuing register reads in STIG mode. This
is needed for example flashes like cypress define in their transaction
table that to read any register there is 1 cmd byte and a few more address
bytes trailing the cmd byte. Absence of addr bytes will obviously fail
to read correct data from flash register that maybe requested by flash
driver because the controller doesn't even specify which address of the
flash register the read is being requested from.

Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index d1f89138ef15bd9db64990da050139bed36e7735..21fe2e655c5f63fda12b2c8744445089598b1c29 100644 (file)
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -479,6 +479,19 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv,
        /* 0 means 1 byte. */
        reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
                << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
+
+       /* setup ADDR BIT field */
+       if (op->addr.nbytes) {
+               writel(op->addr.val, priv->regbase + CQSPI_REG_CMDADDRESS);
+               /*
+                * address bytes are zero indexed
+                */
+               reg |= (((op->addr.nbytes - 1) &
+                         CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
+                         CQSPI_REG_CMDCTRL_ADD_BYTES_LSB);
+               reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
+       }
+
        status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
        if (status != 0)
                return status;